diff options
| author | Andrew Davis <afd@ti.com> | 2024-01-24 21:36:56 +0300 |
|---|---|---|
| committer | Vignesh Raghavendra <vigneshr@ti.com> | 2024-02-05 16:55:57 +0300 |
| commit | 1b63a1b480c27764d30a0924a4982d31e15df6fd (patch) | |
| tree | 54790a2e57f704a849a6b2b8c6d34c2264ea913d | |
| parent | b1898456a4307097c47a340f4a9327a125f75a43 (diff) | |
| download | linux-1b63a1b480c27764d30a0924a4982d31e15df6fd.tar.xz | |
arm64: dts: ti: k3-j7200: Enable PCIe nodes at the board level
PCIe node defined in the top-level J7200 SoC dtsi file is incomplete
and will not be functional unless it is extended with a SerDes PHY.
As the PHY and mode is only known at the board integration level, this
node should only be enabled when provided with this information.
Disable the PCIe node in the dtsi files and only enable when it is
actually pinned out on a given board.
Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20240124183659.149119-1-afd@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
| -rw-r--r-- | arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 1 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index cee2b4b0eb87..7e4fd7ab9750 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -382,6 +382,7 @@ }; &pcie1_rc { + status = "okay"; reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; phys = <&serdes0_pcie_link>; phy-names = "pcie-phy"; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index da67bf8fe703..1e2434caa7ff 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -770,6 +770,7 @@ ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + status = "disabled"; }; pcie1_ep: pcie-ep@2910000 { |