diff options
author | Marc Zyngier <maz@kernel.org> | 2024-02-19 18:13:22 +0300 |
---|---|---|
committer | Catalin Marinas <catalin.marinas@arm.com> | 2024-02-19 19:33:12 +0300 |
commit | 2aea7b77aabc708a9df769ad5fa63e9912ceb7f7 (patch) | |
tree | 659288f5362eb5417479362d9a692b660f8317a7 | |
parent | 90e636f60b76c590aded72964543945084d97c2f (diff) | |
download | linux-2aea7b77aabc708a9df769ad5fa63e9912ceb7f7.tar.xz |
arm64: Use Signed/Unsigned enums for TGRAN{4,16,64} and VARange
Open-coding the feature matching parameters for LVA/LVA2 leads to
issues with upcoming changes to the cpufeature code.
By making TGRAN{4,16,64} and VARange signed/unsigned as per the
architecture, we can use the existing macros, making the feature
match robust against those changes.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Tested-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
-rw-r--r-- | arch/arm64/kernel/cpufeature.c | 15 | ||||
-rw-r--r-- | arch/arm64/tools/sysreg | 8 |
2 files changed, 7 insertions, 16 deletions
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 0be9296e9253..d380ae783b73 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -2706,24 +2706,15 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .capability = ARM64_HAS_VA52, .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, .matches = has_cpuid_feature, - .field_width = 4, #ifdef CONFIG_ARM64_64K_PAGES .desc = "52-bit Virtual Addressing (LVA)", - .sign = FTR_SIGNED, - .sys_reg = SYS_ID_AA64MMFR2_EL1, - .field_pos = ID_AA64MMFR2_EL1_VARange_SHIFT, - .min_field_value = ID_AA64MMFR2_EL1_VARange_52, + ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, VARange, 52) #else .desc = "52-bit Virtual Addressing (LPA2)", - .sys_reg = SYS_ID_AA64MMFR0_EL1, #ifdef CONFIG_ARM64_4K_PAGES - .sign = FTR_SIGNED, - .field_pos = ID_AA64MMFR0_EL1_TGRAN4_SHIFT, - .min_field_value = ID_AA64MMFR0_EL1_TGRAN4_52_BIT, + ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, TGRAN4, 52_BIT) #else - .sign = FTR_UNSIGNED, - .field_pos = ID_AA64MMFR0_EL1_TGRAN16_SHIFT, - .min_field_value = ID_AA64MMFR0_EL1_TGRAN16_52_BIT, + ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, TGRAN16, 52_BIT) #endif #endif }, diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 4c9b67934367..f654e82ef072 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1540,16 +1540,16 @@ Enum 35:32 TGRAN16_2 0b0010 IMP 0b0011 52_BIT EndEnum -Enum 31:28 TGRAN4 +SignedEnum 31:28 TGRAN4 0b0000 IMP 0b0001 52_BIT 0b1111 NI EndEnum -Enum 27:24 TGRAN64 +SignedEnum 27:24 TGRAN64 0b0000 IMP 0b1111 NI EndEnum -Enum 23:20 TGRAN16 +UnsignedEnum 23:20 TGRAN16 0b0000 NI 0b0001 IMP 0b0010 52_BIT @@ -1697,7 +1697,7 @@ Enum 23:20 CCIDX 0b0000 32 0b0001 64 EndEnum -Enum 19:16 VARange +UnsignedEnum 19:16 VARange 0b0000 48 0b0001 52 EndEnum |