diff options
| author | Akhil P Oommen <quic_akhilpo@quicinc.com> | 2024-06-29 04:49:36 +0300 |
|---|---|---|
| committer | Rob Clark <robdclark@chromium.org> | 2024-06-30 02:46:01 +0300 |
| commit | 2c4c53f316f6922211c41ff391ea4eff09e00339 (patch) | |
| tree | 2e2638e7cb074750a4ef4dc01069181a98a55bcc | |
| parent | d6225e0cd096ade35b136a7d2cc5f4f2da63971c (diff) | |
| download | linux-2c4c53f316f6922211c41ff391ea4eff09e00339.tar.xz | |
drm/msm/adreno: Introduce gmu_chipid for a740 & a750
To simplify, introduce the new gmu_chipid for a740 & a750 GPUs.
Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/601396/
Signed-off-by: Rob Clark <robdclark@chromium.org>
| -rw-r--r-- | drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 23 |
2 files changed, 3 insertions, 22 deletions
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c index c507681648ac..bdafca7267a8 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -1206,6 +1206,7 @@ static const struct adreno_info a7xx_gpus[] = { .a6xx = &(const struct a6xx_info) { .hwcg = a740_hwcg, .protect = &a730_protect, + .gmu_chipid = 0x7020100, }, .address_space_size = SZ_16G, }, { @@ -1241,6 +1242,7 @@ static const struct adreno_info a7xx_gpus[] = { .zapfw = "gen70900_zap.mbn", .a6xx = &(const struct a6xx_info) { .protect = &a730_protect, + .gmu_chipid = 0x7090100, }, .address_space_size = SZ_16G, } diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index 400e5cbe4b35..cb538a262d1c 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -769,7 +769,7 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; const struct a6xx_info *a6xx_info = adreno_gpu->info->a6xx; u32 fence_range_lower, fence_range_upper; - u32 chipid, chipid_min = 0; + u32 chipid = 0; int ret; /* Vote veto for FAL10 */ @@ -831,27 +831,6 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) if (a6xx_info->gmu_chipid) { chipid = a6xx_info->gmu_chipid; - /* NOTE: A730 may also fall in this if-condition with a future GMU fw update. */ - } else if (adreno_is_a7xx(adreno_gpu) && !adreno_is_a730(adreno_gpu)) { - /* A7xx GPUs have obfuscated chip IDs. Use constant maj = 7 */ - chipid = FIELD_PREP(GENMASK(31, 24), 0x7); - - /* - * The min part has a 1-1 mapping for each GPU SKU. - * This chipid that the GMU expects corresponds to the "GENX_Y_Z" naming, - * where X = major, Y = minor, Z = patchlevel, e.g. GEN7_2_1 for prod A740. - */ - if (adreno_is_a740(adreno_gpu)) - chipid_min = 2; - else if (adreno_is_a750(adreno_gpu)) - chipid_min = 9; - else - return -EINVAL; - - chipid |= FIELD_PREP(GENMASK(23, 16), chipid_min); - - /* Get the patchid (which may vary) from the device tree */ - chipid |= FIELD_PREP(GENMASK(15, 8), adreno_patchid(adreno_gpu)); } else { /* * Note that the GMU has a slightly different layout for |