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| author | José Roberto de Souza <jose.souza@intel.com> | 2024-04-30 20:28:36 +0300 |
|---|---|---|
| committer | Radhakrishna Sripada <radhakrishna.sripada@intel.com> | 2024-05-03 22:34:04 +0300 |
| commit | 32e73fef7ea2b4728d2580d043613cfeabd90b6c (patch) | |
| tree | 13291e3e9f98ab7fece18c55b274ed3d8f2b0b5b | |
| parent | 68cd73716216f04ef12433a6486821a291736ce3 (diff) | |
| download | linux-32e73fef7ea2b4728d2580d043613cfeabd90b6c.tar.xz | |
drm/i915/xe2hpd: Properly disable power in port A
Xe2_HPD has a different value to power down port A.
BSpec: 65450
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240430172850.1881525-6-radhakrishna.sripada@intel.com
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_cx0_phy.c | 17 |
1 files changed, 14 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index 0444a1ffb030..8621f71e15b4 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -2900,17 +2900,28 @@ void intel_mtl_pll_enable(struct intel_encoder *encoder, intel_cx0pll_enable(encoder, crtc_state); } +static u8 cx0_power_control_disable_val(struct intel_encoder *encoder) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + + if (intel_encoder_is_c10phy(encoder)) + return CX0_P2PG_STATE_DISABLE; + + if (IS_BATTLEMAGE(i915) && encoder->port == PORT_A) + return CX0_P2PG_STATE_DISABLE; + + return CX0_P4PG_STATE_DISABLE; +} + static void intel_cx0pll_disable(struct intel_encoder *encoder) { struct drm_i915_private *i915 = to_i915(encoder->base.dev); enum phy phy = intel_encoder_to_phy(encoder); - bool is_c10 = intel_encoder_is_c10phy(encoder); intel_wakeref_t wakeref = intel_cx0_phy_transaction_begin(encoder); /* 1. Change owned PHY lane power to Disable state. */ intel_cx0_powerdown_change_sequence(encoder, INTEL_CX0_BOTH_LANES, - is_c10 ? CX0_P2PG_STATE_DISABLE : - CX0_P4PG_STATE_DISABLE); + cx0_power_control_disable_val(encoder)); /* * 2. Follow the Display Voltage Frequency Switching Sequence Before |