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author | Lucas De Marchi <lucas.demarchi@intel.com> | 2023-11-21 22:52:09 +0300 |
---|---|---|
committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-12-21 19:45:01 +0300 |
commit | 812ec747a354e00f5e789f3cdcfbc80f98f1d71d (patch) | |
tree | e62f07e525b960aa32c9a0d3d4412c3424f1ffd4 | |
parent | fdb6a05383fab3952c9a56ac716e460134990a69 (diff) | |
download | linux-812ec747a354e00f5e789f3cdcfbc80f98f1d71d.tar.xz |
drm/xe: Sync MTL PCI IDs with i915
For Xe1 platforms, it's better to follow the way i915 adds the PCI IDs
to the header, so it's easier to catch up when there is an update. This
brings the same logic applied in commit 2e3c369f23a7 ("drm/i915/mtl:
Eliminate subplatforms") to the equivalent xe header.
The end result of this header for Xe1 platforms is now in sync with i915
as of commit 5032c607e886 ("drm/i915: ATS-M device ID update"). This can
be seen by
$ git show 5032c607e886:include/drm/i915_pciids.h > a.h
$ git diff --color-words --no-index a.h include/drm/xe_pciids.h
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20231121195209.802235-2-lucas.demarchi@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
-rw-r--r-- | include/drm/xe_pciids.h | 27 |
1 files changed, 4 insertions, 23 deletions
diff --git a/include/drm/xe_pciids.h b/include/drm/xe_pciids.h index 6c3ac3b5ec94..de1a344737bc 100644 --- a/include/drm/xe_pciids.h +++ b/include/drm/xe_pciids.h @@ -173,33 +173,14 @@ XE_ATS_M150_IDS(MACRO__, ## __VA_ARGS__),\ XE_ATS_M75_IDS(MACRO__, ## __VA_ARGS__) -/* MTL */ -#define XE_MTL_M_IDS(MACRO__, ...) \ +/* MTL / ARL */ +#define XE_MTL_IDS(MACRO__, ...) \ MACRO__(0x7D40, ## __VA_ARGS__), \ - MACRO__(0x7D43, ## __VA_ARGS__), \ - MACRO__(0x7DC0, ## __VA_ARGS__) - -#define XE_MTL_P_IDS(MACRO__, ...) \ MACRO__(0x7D45, ## __VA_ARGS__), \ - MACRO__(0x7D47, ## __VA_ARGS__), \ - MACRO__(0x7D50, ## __VA_ARGS__), \ MACRO__(0x7D55, ## __VA_ARGS__), \ - MACRO__(0x7DC5, ## __VA_ARGS__), \ - MACRO__(0x7DD0, ## __VA_ARGS__), \ - MACRO__(0x7DD5, ## __VA_ARGS__) - -#define XE_MTL_S_IDS(MACRO__, ...) \ MACRO__(0x7D60, ## __VA_ARGS__), \ - MACRO__(0x7DE0, ## __VA_ARGS__) - -#define XE_ARL_IDS(MACRO__, ...) \ - MACRO__(0x7D67, ## __VA_ARGS__) - -#define XE_MTL_IDS(MACRO__, ...) \ - XE_MTL_M_IDS(MACRO__, ## __VA_ARGS__), \ - XE_MTL_P_IDS(MACRO__, ## __VA_ARGS__), \ - XE_MTL_S_IDS(MACRO__, ## __VA_ARGS__), \ - XE_ARL_IDS(MACRO__, ## __VA_ARGS__) + MACRO__(0x7D67, ## __VA_ARGS__), \ + MACRO__(0x7DD5, ## __VA_ARGS__) #define XE_LNL_IDS(MACRO__, ...) \ MACRO__(0x6420, ## __VA_ARGS__), \ |