diff options
| author | Matthias Kaehlcke <mka@chromium.org> | 2019-05-16 19:29:40 +0300 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2019-05-20 02:00:20 +0300 |
| commit | 83be81e3b0b6eb5df2fba66baa7a25f7e7dc9775 (patch) | |
| tree | 8b96ae4bfff32324df8db018d1b5632e98d82745 | |
| parent | 1c0479023412ab7834f2e98b796eb0d8c627cd62 (diff) | |
| download | linux-83be81e3b0b6eb5df2fba66baa7a25f7e7dc9775.tar.xz | |
ARM: dts: rockchip: raise CPU trip point temperature for veyron to 100 degC
This value matches what is used by the downstream Chrome OS 3.14
kernel, the 'official' kernel for veyron devices. Keep the temperature
for 'speedy' at 90°C, as in the downstream kernel.
Increase the temperature for a hardware shutdown to 125°C, which
matches the downstream configuration and gives the system a chance
to shut down orderly at the criticial trip point.
Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| -rw-r--r-- | arch/arm/boot/dts/rk3288-veyron-speedy.dts | 4 | ||||
| -rw-r--r-- | arch/arm/boot/dts/rk3288-veyron.dtsi | 5 |
2 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/rk3288-veyron-speedy.dts b/arch/arm/boot/dts/rk3288-veyron-speedy.dts index 2ac8748a3a0c..b07a07e81551 100644 --- a/arch/arm/boot/dts/rk3288-veyron-speedy.dts +++ b/arch/arm/boot/dts/rk3288-veyron-speedy.dts @@ -64,6 +64,10 @@ temperature = <70000>; }; +&cpu_crit { + temperature = <90000>; +}; + &edp { /delete-property/pinctrl-names; /delete-property/pinctrl-0; diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi index 1252522392c7..e81f1a0cac83 100644 --- a/arch/arm/boot/dts/rk3288-veyron.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron.dtsi @@ -123,6 +123,10 @@ cpu0-supply = <&vdd_cpu>; }; +&cpu_crit { + temperature = <100000>; +}; + /* rk3288-c used in Veyron Chrome-devices has slightly changed OPPs */ &cpu_opp_table { /delete-node/ opp-312000000; @@ -394,6 +398,7 @@ rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ + rockchip,hw-tshut-temp = <125000>; }; &uart0 { |