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| author | Lijo Lazar <lijo.lazar@amd.com> | 2023-04-19 13:32:44 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2023-06-09 17:45:23 +0300 |
| commit | a3ffabb25077059427434368a1c65c176a0f93d0 (patch) | |
| tree | 47266df2d037b12d432863392060c9a58aa377ec | |
| parent | d4281b49c1b6afc66c470c85019fc1eceb676a78 (diff) | |
| download | linux-a3ffabb25077059427434368a1c65c176a0f93d0.tar.xz | |
drm/amdgpu: Disable interrupt tracker on NBIOv7.9
Enabling nBIF interrupt history tracker prevents LCLK deep sleep,
hence disable it
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_9_0_offset.h | 2 |
2 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c index ad70086de9b5..e082f6343d20 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c @@ -432,6 +432,8 @@ static void nbio_v7_9_init_registers(struct amdgpu_device *adev) WREG32_SOC15(NBIO, 0, regXCC_DOORBELL_FENCE, 0xff & ~(adev->gfx.xcc_mask)); + WREG32_SOC15(NBIO, 0, regBIFC_GFX_INT_MONITOR_MASK, 0x7ff); + inst_mask = adev->aid_mask & ~1U; for_each_inst(i, inst_mask) { WREG32_SOC15_EXT(NBIO, i, regXCC_DOORBELL_FENCE, i, diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_9_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_9_0_offset.h index 033f2796c1e3..c8a15c8f4822 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_9_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_9_0_offset.h @@ -6201,6 +6201,8 @@ #define regNBIF_SHUB_TODET_SYNCFLOOD_CTRL2_BASE_IDX 8 #define regBIFC_BME_ERR_LOG_HB 0xe8ab #define regBIFC_BME_ERR_LOG_HB_BASE_IDX 8 +#define regBIFC_GFX_INT_MONITOR_MASK 0xe8ad +#define regBIFC_GFX_INT_MONITOR_MASK_BASE_IDX 8 #define regBIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC 0xe8c0 #define regBIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC_BASE_IDX 8 #define regBIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC 0xe8c1 |