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| author | Clint Taylor <clinton.a.taylor@intel.com> | 2023-05-16 02:17:24 +0300 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2023-05-19 20:02:34 +0300 |
| commit | cb7b04c83e9006c39af6d806761fc628573920e8 (patch) | |
| tree | 04b6a57f52f53f31b03e58595951bfe5798862bf | |
| parent | 615ed9ece01814a94fb544226cb3f4e03f06851d (diff) | |
| download | linux-cb7b04c83e9006c39af6d806761fc628573920e8.tar.xz | |
drm/i915: Add 16bit register/mask operators
Add the support macros to define/extract bits as 16bits.
v2: checkpatch fixes
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230515231725.3815199-2-clinton.a.taylor@intel.com
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg_defs.h | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h b/drivers/gpu/drm/i915/i915_reg_defs.h index 622d603080f9..a685db1e815d 100644 --- a/drivers/gpu/drm/i915/i915_reg_defs.h +++ b/drivers/gpu/drm/i915/i915_reg_defs.h @@ -143,6 +143,54 @@ */ #define REG_FIELD_GET64(__mask, __val) ((u64)FIELD_GET(__mask, __val)) +/** + * REG_BIT16() - Prepare a u16 bit value + * @__n: 0-based bit number + * + * Local wrapper for BIT() to force u16, with compile time + * checks. + * + * @return: Value with bit @__n set. + */ +#define REG_BIT16(__n) \ + ((u16)(BIT(__n) + \ + BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \ + ((__n) < 0 || (__n) > 15)))) + +/** + * REG_GENMASK16() - Prepare a continuous u8 bitmask + * @__high: 0-based high bit + * @__low: 0-based low bit + * + * Local wrapper for GENMASK() to force u16, with compile time + * checks. + * + * @return: Continuous bitmask from @__high to @__low, inclusive. + */ +#define REG_GENMASK16(__high, __low) \ + ((u16)(GENMASK(__high, __low) + \ + BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \ + __is_constexpr(__low) && \ + ((__low) < 0 || (__high) > 15 || (__low) > (__high))))) + +/** + * REG_FIELD_PREP16() - Prepare a u16 bitfield value + * @__mask: shifted mask defining the field's length and position + * @__val: value to put in the field + * + * Local copy of FIELD_PREP16() to generate an integer constant + * expression, force u8 and for consistency with + * REG_FIELD_GET16(), REG_BIT16() and REG_GENMASK16(). + * + * @return: @__val masked and shifted into the field defined by @__mask. + */ +#define REG_FIELD_PREP16(__mask, __val) \ + ((u16)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \ + BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \ + BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U16_MAX) + \ + BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \ + BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0)))) + #define __MASKED_FIELD(mask, value) ((mask) << 16 | (value)) #define _MASKED_FIELD(mask, value) ({ \ if (__builtin_constant_p(mask)) \ |