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authorMiquel Raynal <miquel.raynal@bootlin.com>2022-01-27 12:18:06 +0300
committerMiquel Raynal <miquel.raynal@bootlin.com>2022-02-10 11:32:30 +0300
commitd1b64bb28907b0ae4eff6befd6a1a476fbb68424 (patch)
tree5e8ac316edaf8d5f6bbc009c1cdc74fc3bbbcd72
parentb7b64db74ea53f51d316077c1267bb4d0792ef4b (diff)
downloadlinux-d1b64bb28907b0ae4eff6befd6a1a476fbb68424.tar.xz
spi: mxic: Create a helper to ease the start of an operation
Create the mxic_spi_mem_prep_op_cfg() helper to provide the content to write to the register controlling the next IO command. This helper will soon be used by the dirmap implementation and having this code factorized out earlier will clarify this addition. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-12-miquel.raynal@bootlin.com
-rw-r--r--drivers/spi/spi-mxic.c53
1 files changed, 29 insertions, 24 deletions
diff --git a/drivers/spi/spi-mxic.c b/drivers/spi/spi-mxic.c
index c45f949a864d..ba9cda4bf161 100644
--- a/drivers/spi/spi-mxic.c
+++ b/drivers/spi/spi-mxic.c
@@ -296,6 +296,33 @@ static u32 mxic_spi_prep_hc_cfg(struct spi_device *spi, u32 flags)
HC_CFG_SLV_ACT(spi->chip_select) | HC_CFG_IDLE_SIO_LVL(1);
}
+static u32 mxic_spi_mem_prep_op_cfg(const struct spi_mem_op *op)
+{
+ u32 cfg = OP_CMD_BYTES(op->cmd.nbytes) |
+ OP_CMD_BUSW(fls(op->cmd.buswidth) - 1) |
+ (op->cmd.dtr ? OP_CMD_DDR : 0);
+
+ if (op->addr.nbytes)
+ cfg |= OP_ADDR_BYTES(op->addr.nbytes) |
+ OP_ADDR_BUSW(fls(op->addr.buswidth) - 1) |
+ (op->addr.dtr ? OP_ADDR_DDR : 0);
+
+ if (op->dummy.nbytes)
+ cfg |= OP_DUMMY_CYC(op->dummy.nbytes);
+
+ if (op->data.nbytes) {
+ cfg |= OP_DATA_BUSW(fls(op->data.buswidth) - 1) |
+ (op->data.dtr ? OP_DATA_DDR : 0);
+ if (op->data.dir == SPI_MEM_DATA_IN) {
+ cfg |= OP_READ;
+ if (op->data.dtr)
+ cfg |= OP_DQS_EN;
+ }
+ }
+
+ return cfg;
+}
+
static int mxic_spi_data_xfer(struct mxic_spi *mxic, const void *txbuf,
void *rxbuf, unsigned int len)
{
@@ -366,7 +393,6 @@ static int mxic_spi_mem_exec_op(struct spi_mem *mem,
{
struct mxic_spi *mxic = spi_master_get_devdata(mem->spi->master);
int i, ret;
- u32 ss_ctrl;
u8 addr[8], cmd[2];
ret = mxic_spi_set_freq(mxic, mem->spi->max_speed_hz);
@@ -378,29 +404,8 @@ static int mxic_spi_mem_exec_op(struct spi_mem *mem,
writel(HC_EN_BIT, mxic->regs + HC_EN);
- ss_ctrl = OP_CMD_BYTES(op->cmd.nbytes) |
- OP_CMD_BUSW(fls(op->cmd.buswidth) - 1) |
- (op->cmd.dtr ? OP_CMD_DDR : 0);
-
- if (op->addr.nbytes)
- ss_ctrl |= OP_ADDR_BYTES(op->addr.nbytes) |
- OP_ADDR_BUSW(fls(op->addr.buswidth) - 1) |
- (op->addr.dtr ? OP_ADDR_DDR : 0);
-
- if (op->dummy.nbytes)
- ss_ctrl |= OP_DUMMY_CYC(op->dummy.nbytes);
-
- if (op->data.nbytes) {
- ss_ctrl |= OP_DATA_BUSW(fls(op->data.buswidth) - 1) |
- (op->data.dtr ? OP_DATA_DDR : 0);
- if (op->data.dir == SPI_MEM_DATA_IN) {
- ss_ctrl |= OP_READ;
- if (op->data.dtr)
- ss_ctrl |= OP_DQS_EN;
- }
- }
-
- writel(ss_ctrl, mxic->regs + SS_CTRL(mem->spi->chip_select));
+ writel(mxic_spi_mem_prep_op_cfg(op),
+ mxic->regs + SS_CTRL(mem->spi->chip_select));
writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_ASSERT,
mxic->regs + HC_CFG);