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authorDavid S. Miller <davem@davemloft.net>2024-03-01 11:56:39 +0300
committerDavid S. Miller <davem@davemloft.net>2024-03-01 11:56:39 +0300
commitfc809e1e5390d017884a1217fc77577fdf76fe56 (patch)
tree3d4fe1cbe6f447342b980cf599adf52dfc561d75
parentf29f9199c2d2b3c258f577f438885288016847ed (diff)
parentcb28f702960695e26597c332b0e46776e825cc34 (diff)
downloadlinux-fc809e1e5390d017884a1217fc77577fdf76fe56.tar.xz
Merge branch 'qcom-phy-possible'
Robert Marko says: ==================== net: phy: qcom: qca808x: fill in possible_interfaces QCA808x does not currently fill in the possible_interfaces. This leads to Phylink not being aware that it supports 2500Base-X as well so in cases where it is connected to a DSA switch like MV88E6393 it will limit that port to phy-mode set in the DTS. That means that if SGMII is used you are limited to 1G only while if 2500Base-X was set you are limited to 2.5G only. Populating the possible_interfaces fixes this. Changes in v2: * Get rid of the if/else by Russels suggestion in the helper ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r--drivers/net/phy/qcom/qca808x.c29
1 files changed, 24 insertions, 5 deletions
diff --git a/drivers/net/phy/qcom/qca808x.c b/drivers/net/phy/qcom/qca808x.c
index 2acf852fb4de..5048304ccc9e 100644
--- a/drivers/net/phy/qcom/qca808x.c
+++ b/drivers/net/phy/qcom/qca808x.c
@@ -156,6 +156,27 @@ static bool qca808x_has_fast_retrain_or_slave_seed(struct phy_device *phydev)
return linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported);
}
+static bool qca808x_is_1g_only(struct phy_device *phydev)
+{
+ int ret;
+
+ ret = phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_CHIP_TYPE);
+ if (ret < 0)
+ return true;
+
+ return !!(QCA808X_PHY_CHIP_TYPE_1G & ret);
+}
+
+static void qca808x_fill_possible_interfaces(struct phy_device *phydev)
+{
+ unsigned long *possible = phydev->possible_interfaces;
+
+ __set_bit(PHY_INTERFACE_MODE_SGMII, possible);
+
+ if (!qca808x_is_1g_only(phydev))
+ __set_bit(PHY_INTERFACE_MODE_2500BASEX, possible);
+}
+
static int qca808x_probe(struct phy_device *phydev)
{
struct device *dev = &phydev->mdio.dev;
@@ -220,6 +241,8 @@ static int qca808x_config_init(struct phy_device *phydev)
}
}
+ qca808x_fill_possible_interfaces(phydev);
+
/* Configure adc threshold as 100mv for the link 10M */
return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_ADC_THRESHOLD,
QCA808X_ADC_THRESHOLD_MASK,
@@ -350,11 +373,7 @@ static int qca808x_get_features(struct phy_device *phydev)
* existed in the bit0 of MMD1.21, we need to remove it manually if
* it is the qca8081 1G chip according to the bit0 of MMD7.0x901d.
*/
- ret = phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_CHIP_TYPE);
- if (ret < 0)
- return ret;
-
- if (QCA808X_PHY_CHIP_TYPE_1G & ret)
+ if (qca808x_is_1g_only(phydev))
linkmode_clear_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported);
return 0;