diff options
author | Ben Skeggs <bskeggs@redhat.com> | 2020-06-22 09:20:32 +0300 |
---|---|---|
committer | Ben Skeggs <bskeggs@redhat.com> | 2020-07-24 11:50:57 +0300 |
commit | fe4249afd6a94363e2ef7334d5257171da474bb6 (patch) | |
tree | 0d96a106f1fc975cc684af721e2a5dd33a2403e7 | |
parent | 01c43a66eb7aac48b3a978158cfb45674b18a48e (diff) | |
download | linux-fe4249afd6a94363e2ef7334d5257171da474bb6.tar.xz |
drm/nouveau/bo: convert move move() to new push macros
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_bo0039.c | 31 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_bo5039.c | 65 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_bo74c1.c | 27 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_bo85b5.c | 25 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_bo9039.c | 24 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_bo90b5.c | 25 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_boa0b5.c | 31 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_dma.h | 17 |
8 files changed, 114 insertions, 131 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo0039.c b/drivers/gpu/drm/nouveau/nouveau_bo0039.c index ddf2f5ee1140..e00ec7cfce5f 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo0039.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo0039.c @@ -45,39 +45,36 @@ int nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) { + struct nvif_push *push = chan->chan.push; u32 src_offset = old_reg->start << PAGE_SHIFT; u32 dst_offset = new_reg->start << PAGE_SHIFT; u32 page_count = new_reg->num_pages; int ret; - ret = RING_SPACE(chan, 3); + ret = PUSH_WAIT(push, 3); if (ret) return ret; - BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2); - OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, old_reg)); - OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, new_reg)); + PUSH_NVSQ(push, NV039, 0x0184, nouveau_bo_mem_ctxdma(bo, chan, old_reg), + 0x0188, nouveau_bo_mem_ctxdma(bo, chan, new_reg)); page_count = new_reg->num_pages; while (page_count) { int line_count = (page_count > 2047) ? 2047 : page_count; - ret = RING_SPACE(chan, 11); + ret = PUSH_WAIT(push, 11); if (ret) return ret; - BEGIN_NV04(chan, NvSubCopy, - NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8); - OUT_RING (chan, src_offset); - OUT_RING (chan, dst_offset); - OUT_RING (chan, PAGE_SIZE); /* src_pitch */ - OUT_RING (chan, PAGE_SIZE); /* dst_pitch */ - OUT_RING (chan, PAGE_SIZE); /* line_length */ - OUT_RING (chan, line_count); - OUT_RING (chan, 0x00000101); - OUT_RING (chan, 0x00000000); - BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1); - OUT_RING (chan, 0); + PUSH_NVSQ(push, NV039, 0x030c, src_offset, + 0x0310, dst_offset, + 0x0314, PAGE_SIZE, /* src_pitch */ + 0x0318, PAGE_SIZE, /* dst_pitch */ + 0x031c, PAGE_SIZE, /* line_length */ + 0x0320, line_count, + 0x0324, 0x00000101, + 0x0328, 0x00000000); + PUSH_NVSQ(push, NV039, 0x0100, 0x00000000); page_count -= line_count; src_offset += (PAGE_SIZE * line_count); diff --git a/drivers/gpu/drm/nouveau/nouveau_bo5039.c b/drivers/gpu/drm/nouveau/nouveau_bo5039.c index 9a667dc93dd3..19fb36b35ff9 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo5039.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo5039.c @@ -38,6 +38,7 @@ nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) { struct nouveau_mem *mem = nouveau_mem(old_reg); + struct nvif_push *push = chan->chan.push; u64 length = (new_reg->num_pages << PAGE_SHIFT); u64 src_offset = mem->vma[0].addr; u64 dst_offset = mem->vma[1].addr; @@ -48,7 +49,7 @@ nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, while (length) { u32 amount, stride, height; - ret = RING_SPACE(chan, 18 + 6 * (src_tiled + dst_tiled)); + ret = PUSH_WAIT(push, 18 + 6 * (src_tiled + dst_tiled)); if (ret) return ret; @@ -57,46 +58,40 @@ nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, height = amount / stride; if (src_tiled) { - BEGIN_NV04(chan, NvSubCopy, 0x0200, 7); - OUT_RING (chan, 0); - OUT_RING (chan, 0); - OUT_RING (chan, stride); - OUT_RING (chan, height); - OUT_RING (chan, 1); - OUT_RING (chan, 0); - OUT_RING (chan, 0); + PUSH_NVSQ(push, NV5039, 0x0200, 0, + 0x0204, 0, + 0x0208, stride, + 0x020c, height, + 0x0210, 1, + 0x0214, 0, + 0x0218, 0); } else { - BEGIN_NV04(chan, NvSubCopy, 0x0200, 1); - OUT_RING (chan, 1); + PUSH_NVSQ(push, NV5039, 0x0200, 1); } + if (dst_tiled) { - BEGIN_NV04(chan, NvSubCopy, 0x021c, 7); - OUT_RING (chan, 0); - OUT_RING (chan, 0); - OUT_RING (chan, stride); - OUT_RING (chan, height); - OUT_RING (chan, 1); - OUT_RING (chan, 0); - OUT_RING (chan, 0); + PUSH_NVSQ(push, NV5039, 0x021c, 0, + 0x0220, 0, + 0x0224, stride, + 0x0228, height, + 0x022c, 1, + 0x0230, 0, + 0x0234, 0); } else { - BEGIN_NV04(chan, NvSubCopy, 0x021c, 1); - OUT_RING (chan, 1); + PUSH_NVSQ(push, NV5039, 0x021c, 1); } - BEGIN_NV04(chan, NvSubCopy, 0x0238, 2); - OUT_RING (chan, upper_32_bits(src_offset)); - OUT_RING (chan, upper_32_bits(dst_offset)); - BEGIN_NV04(chan, NvSubCopy, 0x030c, 8); - OUT_RING (chan, lower_32_bits(src_offset)); - OUT_RING (chan, lower_32_bits(dst_offset)); - OUT_RING (chan, stride); - OUT_RING (chan, stride); - OUT_RING (chan, stride); - OUT_RING (chan, height); - OUT_RING (chan, 0x00000101); - OUT_RING (chan, 0x00000000); - BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1); - OUT_RING (chan, 0); + PUSH_NVSQ(push, NV5039, 0x0238, upper_32_bits(src_offset), + 0x023c, upper_32_bits(dst_offset)); + PUSH_NVSQ(push, NV5039, 0x030c, lower_32_bits(src_offset), + 0x0310, lower_32_bits(dst_offset), + 0x0314, stride, + 0x0318, stride, + 0x031c, stride, + 0x0320, height, + 0x0324, 0x00000101, + 0x0328, 0x00000000); + PUSH_NVSQ(push, NV5039, 0x0100, 0x00000000); length -= amount; src_offset += amount; diff --git a/drivers/gpu/drm/nouveau/nouveau_bo74c1.c b/drivers/gpu/drm/nouveau/nouveau_bo74c1.c index 7528a03229b2..1b5fd78ddcba 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo74c1.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo74c1.c @@ -30,20 +30,25 @@ #include "nouveau_dma.h" #include "nouveau_mem.h" +#include <nvif/push206e.h> + int nv84_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo, struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) { struct nouveau_mem *mem = nouveau_mem(old_reg); - int ret = RING_SPACE(chan, 7); - if (ret == 0) { - BEGIN_NV04(chan, NvSubCopy, 0x0304, 6); - OUT_RING (chan, new_reg->num_pages << PAGE_SHIFT); - OUT_RING (chan, upper_32_bits(mem->vma[0].addr)); - OUT_RING (chan, lower_32_bits(mem->vma[0].addr)); - OUT_RING (chan, upper_32_bits(mem->vma[1].addr)); - OUT_RING (chan, lower_32_bits(mem->vma[1].addr)); - OUT_RING (chan, 0x00000000 /* MODE_COPY, QUERY_NONE */); - } - return ret; + struct nvif_push *push = chan->chan.push; + int ret; + + ret = PUSH_WAIT(push, 7); + if (ret) + return ret; + + PUSH_NVSQ(push, NV74C1, 0x0304, new_reg->num_pages << PAGE_SHIFT, + 0x0308, upper_32_bits(mem->vma[0].addr), + 0x030c, lower_32_bits(mem->vma[0].addr), + 0x0310, upper_32_bits(mem->vma[1].addr), + 0x0314, lower_32_bits(mem->vma[1].addr), + 0x0318, 0x00000000 /* MODE_COPY, QUERY_NONE */); + return 0; } diff --git a/drivers/gpu/drm/nouveau/nouveau_bo85b5.c b/drivers/gpu/drm/nouveau/nouveau_bo85b5.c index c658c5e5fe04..f0df172b029e 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo85b5.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo85b5.c @@ -30,6 +30,8 @@ #include "nouveau_dma.h" #include "nouveau_mem.h" +#include <nvif/push206e.h> + /*XXX: Fixup class to be compatible with NVIDIA's, which will allow sharing * code with KeplerDmaCopyA. */ @@ -39,6 +41,7 @@ nva3_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) { struct nouveau_mem *mem = nouveau_mem(old_reg); + struct nvif_push *push = chan->chan.push; u64 src_offset = mem->vma[0].addr; u64 dst_offset = mem->vma[1].addr; u32 page_count = new_reg->num_pages; @@ -48,21 +51,19 @@ nva3_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, while (page_count) { int line_count = (page_count > 8191) ? 8191 : page_count; - ret = RING_SPACE(chan, 11); + ret = PUSH_WAIT(push, 11); if (ret) return ret; - BEGIN_NV04(chan, NvSubCopy, 0x030c, 8); - OUT_RING (chan, upper_32_bits(src_offset)); - OUT_RING (chan, lower_32_bits(src_offset)); - OUT_RING (chan, upper_32_bits(dst_offset)); - OUT_RING (chan, lower_32_bits(dst_offset)); - OUT_RING (chan, PAGE_SIZE); - OUT_RING (chan, PAGE_SIZE); - OUT_RING (chan, PAGE_SIZE); - OUT_RING (chan, line_count); - BEGIN_NV04(chan, NvSubCopy, 0x0300, 1); - OUT_RING (chan, 0x00000110); + PUSH_NVSQ(push, NV85B5, 0x030c, upper_32_bits(src_offset), + 0x0310, lower_32_bits(src_offset), + 0x0314, upper_32_bits(dst_offset), + 0x0318, lower_32_bits(dst_offset), + 0x031c, PAGE_SIZE, + 0x0320, PAGE_SIZE, + 0x0324, PAGE_SIZE, + 0x0328, line_count); + PUSH_NVSQ(push, NV85B5, 0x0300, 0x00000110); page_count -= line_count; src_offset += (PAGE_SIZE * line_count); diff --git a/drivers/gpu/drm/nouveau/nouveau_bo9039.c b/drivers/gpu/drm/nouveau/nouveau_bo9039.c index f9ba04faf1a2..995ebe7ffe00 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo9039.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo9039.c @@ -36,6 +36,7 @@ int nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) { + struct nvif_push *push = chan->chan.push; struct nouveau_mem *mem = nouveau_mem(old_reg); u64 src_offset = mem->vma[0].addr; u64 dst_offset = mem->vma[1].addr; @@ -46,22 +47,19 @@ nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, while (page_count) { int line_count = (page_count > 2047) ? 2047 : page_count; - ret = RING_SPACE(chan, 12); + ret = PUSH_WAIT(push, 12); if (ret) return ret; - BEGIN_NVC0(chan, NvSubCopy, 0x0238, 2); - OUT_RING (chan, upper_32_bits(dst_offset)); - OUT_RING (chan, lower_32_bits(dst_offset)); - BEGIN_NVC0(chan, NvSubCopy, 0x030c, 6); - OUT_RING (chan, upper_32_bits(src_offset)); - OUT_RING (chan, lower_32_bits(src_offset)); - OUT_RING (chan, PAGE_SIZE); /* src_pitch */ - OUT_RING (chan, PAGE_SIZE); /* dst_pitch */ - OUT_RING (chan, PAGE_SIZE); /* line_length */ - OUT_RING (chan, line_count); - BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1); - OUT_RING (chan, 0x00100110); + PUSH_NVSQ(push, NV9039, 0x0238, upper_32_bits(dst_offset), + 0x023c, lower_32_bits(dst_offset)); + PUSH_NVSQ(push, NV9039, 0x030c, upper_32_bits(src_offset), + 0x0310, lower_32_bits(src_offset), + 0x0314, PAGE_SIZE, /* src_pitch */ + 0x0318, PAGE_SIZE, /* dst_pitch */ + 0x031c, PAGE_SIZE, /* line_length */ + 0x0320, line_count); + PUSH_NVSQ(push, NV9039, 0x0300, 0x00100110); page_count -= line_count; src_offset += (PAGE_SIZE * line_count); diff --git a/drivers/gpu/drm/nouveau/nouveau_bo90b5.c b/drivers/gpu/drm/nouveau/nouveau_bo90b5.c index 4c014f9a641f..34b79d561c7f 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo90b5.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo90b5.c @@ -23,6 +23,8 @@ #include "nouveau_dma.h" #include "nouveau_mem.h" +#include <nvif/push906f.h> + /*XXX: Fixup class to be compatible with NVIDIA's, which will allow sharing * code with KeplerDmaCopyA. */ @@ -32,6 +34,7 @@ nvc0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) { struct nouveau_mem *mem = nouveau_mem(old_reg); + struct nvif_push *push = chan->chan.push; u64 src_offset = mem->vma[0].addr; u64 dst_offset = mem->vma[1].addr; u32 page_count = new_reg->num_pages; @@ -41,21 +44,19 @@ nvc0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, while (page_count) { int line_count = (page_count > 8191) ? 8191 : page_count; - ret = RING_SPACE(chan, 11); + ret = PUSH_WAIT(push, 10); if (ret) return ret; - BEGIN_NVC0(chan, NvSubCopy, 0x030c, 8); - OUT_RING (chan, upper_32_bits(src_offset)); - OUT_RING (chan, lower_32_bits(src_offset)); - OUT_RING (chan, upper_32_bits(dst_offset)); - OUT_RING (chan, lower_32_bits(dst_offset)); - OUT_RING (chan, PAGE_SIZE); - OUT_RING (chan, PAGE_SIZE); - OUT_RING (chan, PAGE_SIZE); - OUT_RING (chan, line_count); - BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1); - OUT_RING (chan, 0x00000110); + PUSH_NVSQ(push, NV90B5, 0x030c, upper_32_bits(src_offset), + 0x0310, lower_32_bits(src_offset), + 0x0314, upper_32_bits(dst_offset), + 0x0318, lower_32_bits(dst_offset), + 0x031c, PAGE_SIZE, + 0x0320, PAGE_SIZE, + 0x0324, PAGE_SIZE, + 0x0328, line_count); + PUSH_NVIM(push, NV90B5, 0x0300, 0x0110); page_count -= line_count; src_offset += (PAGE_SIZE * line_count); diff --git a/drivers/gpu/drm/nouveau/nouveau_boa0b5.c b/drivers/gpu/drm/nouveau/nouveau_boa0b5.c index 9c09691623d0..b1afb2724fb7 100644 --- a/drivers/gpu/drm/nouveau/nouveau_boa0b5.c +++ b/drivers/gpu/drm/nouveau/nouveau_boa0b5.c @@ -37,20 +37,23 @@ nve0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) { struct nouveau_mem *mem = nouveau_mem(old_reg); - int ret = RING_SPACE(chan, 10); - if (ret == 0) { - BEGIN_NVC0(chan, NvSubCopy, 0x0400, 8); - OUT_RING (chan, upper_32_bits(mem->vma[0].addr)); - OUT_RING (chan, lower_32_bits(mem->vma[0].addr)); - OUT_RING (chan, upper_32_bits(mem->vma[1].addr)); - OUT_RING (chan, lower_32_bits(mem->vma[1].addr)); - OUT_RING (chan, PAGE_SIZE); - OUT_RING (chan, PAGE_SIZE); - OUT_RING (chan, PAGE_SIZE); - OUT_RING (chan, new_reg->num_pages); - BEGIN_IMC0(chan, NvSubCopy, 0x0300, 0x0386); - } - return ret; + struct nvif_push *push = chan->chan.push; + int ret; + + ret = PUSH_WAIT(push, 10); + if (ret) + return ret; + + PUSH_NVSQ(push, NVA0B5, 0x0400, upper_32_bits(mem->vma[0].addr), + 0x0404, lower_32_bits(mem->vma[0].addr), + 0x0408, upper_32_bits(mem->vma[1].addr), + 0x040c, lower_32_bits(mem->vma[1].addr), + 0x0410, PAGE_SIZE, + 0x0414, PAGE_SIZE, + 0x0418, PAGE_SIZE, + 0x041c, new_reg->num_pages); + PUSH_NVIM(push, NVA0B5, 0x0300, 0x0386); + return 0; } int diff --git a/drivers/gpu/drm/nouveau/nouveau_dma.h b/drivers/gpu/drm/nouveau/nouveau_dma.h index 72de20437542..8778fd6002c0 100644 --- a/drivers/gpu/drm/nouveau/nouveau_dma.h +++ b/drivers/gpu/drm/nouveau/nouveau_dma.h @@ -63,23 +63,6 @@ enum { NvEvoSema1 = 0x80000011, }; -#define NV_MEMORY_TO_MEMORY_FORMAT 0x00000039 -#define NV_MEMORY_TO_MEMORY_FORMAT_NAME 0x00000000 -#define NV_MEMORY_TO_MEMORY_FORMAT_SET_REF 0x00000050 -#define NV_MEMORY_TO_MEMORY_FORMAT_NOP 0x00000100 -#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY 0x00000104 -#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY_STYLE_WRITE 0x00000000 -#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY_STYLE_WRITE_LE_AWAKEN 0x00000001 -#define NV_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY 0x00000180 -#define NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE 0x00000184 -#define NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN 0x0000030c - -#define NV50_MEMORY_TO_MEMORY_FORMAT 0x00005039 -#define NV50_MEMORY_TO_MEMORY_FORMAT_UNK200 0x00000200 -#define NV50_MEMORY_TO_MEMORY_FORMAT_UNK21C 0x0000021c -#define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN_HIGH 0x00000238 -#define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_OUT_HIGH 0x0000023c - static __must_check inline int RING_SPACE(struct nouveau_channel *chan, int size) { |