diff options
| author | Dan Williams <dan.j.williams@intel.com> | 2023-02-07 22:12:24 +0300 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2023-02-07 22:12:24 +0300 |
| commit | 5485eb955994a238eafd08d9266005b1c9ac7991 (patch) | |
| tree | fad2a31e1f9340de6aecbec16fa18509409ff5d1 /Documentation/ABI | |
| parent | 711442e29f16f0d39dd0e2460c9baacfccb9d5a7 (diff) | |
| parent | 623c0751336e4035ab0047f2c152a02bd26b612b (diff) | |
| download | linux-5485eb955994a238eafd08d9266005b1c9ac7991.tar.xz | |
Merge branch 'for-6.3/cxl' into cxl/next
Merge the general CXL updates with fixes targeting v6.2-rc for v6.3.
Resolve a conflict with the fix and move of cxl_report_and_clear() from
pci.c to core/pci.c.
Diffstat (limited to 'Documentation/ABI')
| -rw-r--r-- | Documentation/ABI/testing/sysfs-bus-cxl | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/Documentation/ABI/testing/sysfs-bus-cxl b/Documentation/ABI/testing/sysfs-bus-cxl index 8494ef27e8d2..329a7e46c805 100644 --- a/Documentation/ABI/testing/sysfs-bus-cxl +++ b/Documentation/ABI/testing/sysfs-bus-cxl @@ -90,6 +90,21 @@ Description: capability. +What: /sys/bus/cxl/devices/{port,endpoint}X/parent_dport +Date: January, 2023 +KernelVersion: v6.3 +Contact: linux-cxl@vger.kernel.org +Description: + (RO) CXL port objects are instantiated for each upstream port in + a CXL/PCIe switch, and for each endpoint to map the + corresponding memory device into the CXL port hierarchy. When a + descendant CXL port (switch or endpoint) is enumerated it is + useful to know which 'dport' object in the parent CXL port + routes to this descendant. The 'parent_dport' symlink points to + the device representing the downstream port of a CXL switch that + routes to {port,endpoint}X. + + What: /sys/bus/cxl/devices/portX/dportY Date: June, 2021 KernelVersion: v5.14 |