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authorTamar Mashiah <tamar.mashiah@intel.com>2021-04-11 17:15:32 +0300
committerHans de Goede <hdegoede@redhat.com>2021-04-13 10:26:40 +0300
commitee7abc105e2b30378187e520be458a127d1d3762 (patch)
tree70e57d2d1459c9190223079d91cbd9aed0bd07f1 /Documentation/ABI
parent6759e18e5cd8745a5dfc5726e4a3db5281ec1639 (diff)
downloadlinux-ee7abc105e2b30378187e520be458a127d1d3762.tar.xz
platform/x86: intel_pmc_core: export platform global reset bits via etr3 sysfs file
During PCH (platform/board) manufacturing process a global platform reset has to be induced in order for the configuration changes take the effect upon following platform reset. This is an internal platform state and is not intended to be used in the regular platform resets. The setting is exposed via ETR3 (Extended Test Mode Register 3). After the manufacturing process is completed the register cannot be written anymore and is hardware locked. This setting was commonly done by accessing PMC registers via /dev/mem but due to security concerns /dev/mem access is much more restricted, hence the reason for exposing this setting via the dedicated sysfs interface. To prevent post manufacturing abuse the register is protected by hardware locking and the file is set to read-only mode via is_visible handler. The register in MMIO space is defined for Cannon Lake and newer PCHs. Cc: Hans de Goede <hdegoede@redhat.com> Cc: David E Box <david.e.box@intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Tamar Mashiah <tamar.mashiah@intel.com> Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> Link: https://lore.kernel.org/r/20210411141532.3004893-1-tomas.winkler@intel.com Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Diffstat (limited to 'Documentation/ABI')
-rw-r--r--Documentation/ABI/testing/sysfs-platform-intel-pmc20
1 files changed, 20 insertions, 0 deletions
diff --git a/Documentation/ABI/testing/sysfs-platform-intel-pmc b/Documentation/ABI/testing/sysfs-platform-intel-pmc
new file mode 100644
index 000000000000..ef199af75ab0
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-platform-intel-pmc
@@ -0,0 +1,20 @@
+What: /sys/devices/platform/<platform>/etr3
+Date: Apr 2021
+KernelVersion: 5.13
+Contact: "Tomas Winkler" <tomas.winkler@intel.com>
+Description:
+ The file exposes "Extended Test Mode Register 3" global
+ reset bits. The bits are used during an Intel platform
+ manufacturing process to indicate that consequent reset
+ of the platform is a "global reset". This type of reset
+ is required in order for manufacturing configurations
+ to take effect.
+
+ Display global reset setting bits for PMC.
+ * bit 31 - global reset is locked
+ * bit 20 - global reset is set
+ Writing bit 20 value to the etr3 will induce
+ a platform "global reset" upon consequent platform reset,
+ in case the register is not locked.
+ The "global reset bit" should be locked on a production
+ system and the file is in read-only mode.