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authorHuacai Chen <chenhuacai@loongson.cn>2023-04-18 14:38:58 +0300
committerHuacai Chen <chenhuacai@loongson.cn>2023-04-18 14:38:58 +0300
commit16c52e503043aed1e2a2ce38d9249de5936c1f6b (patch)
tree7552a1e276d52b2cff4da4e8c7a0be030d4ce77a /Documentation/admin-guide/kernel-parameters.rst
parent6a8f57ae2eb07ab39a6f0ccad60c760743051026 (diff)
downloadlinux-16c52e503043aed1e2a2ce38d9249de5936c1f6b.tar.xz
LoongArch: Make WriteCombine configurable for ioremap()
LoongArch maintains cache coherency in hardware, but when paired with LS7A chipsets the WUC attribute (Weak-ordered UnCached, which is similar to WriteCombine) is out of the scope of cache coherency machanism for PCIe devices (this is a PCIe protocol violation, which may be fixed in newer chipsets). This means WUC can only used for write-only memory regions now, so this option is disabled by default, making WUC silently fallback to SUC for ioremap(). You can enable this option if the kernel is ensured to run on hardware without this bug. Kernel parameter writecombine=on/off can be used to override the Kconfig option. Cc: stable@vger.kernel.org Suggested-by: WANG Xuerui <kernel@xen0n.name> Reviewed-by: WANG Xuerui <kernel@xen0n.name> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
Diffstat (limited to 'Documentation/admin-guide/kernel-parameters.rst')
-rw-r--r--Documentation/admin-guide/kernel-parameters.rst1
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diff --git a/Documentation/admin-guide/kernel-parameters.rst b/Documentation/admin-guide/kernel-parameters.rst
index 19600c50277b..6ae5f129fbca 100644
--- a/Documentation/admin-guide/kernel-parameters.rst
+++ b/Documentation/admin-guide/kernel-parameters.rst
@@ -128,6 +128,7 @@ parameter is applicable::
KVM Kernel Virtual Machine support is enabled.
LIBATA Libata driver is enabled
LP Printer support is enabled.
+ LOONGARCH LoongArch architecture is enabled.
LOOP Loopback device support is enabled.
M68k M68k architecture is enabled.
These options have more detailed description inside of