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author | Mauro Carvalho Chehab <mchehab+samsung@kernel.org> | 2019-06-18 22:06:08 +0300 |
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committer | Mauro Carvalho Chehab <mchehab+samsung@kernel.org> | 2019-07-15 15:20:27 +0300 |
commit | 59809fe88224db24432ad50e62fd8d5f0df738a1 (patch) | |
tree | 5adaab915e2053421f0658e12f9f6b75016ef8f5 /Documentation/admin-guide/perf/qcom_l2_pmu.rst | |
parent | d2bdd48a652bd0f7a5c78f3e418b4529fc469e1f (diff) | |
download | linux-59809fe88224db24432ad50e62fd8d5f0df738a1.tar.xz |
docs: perf: move to the admin-guide
The perf infrastructure is used for userspace to track issues.
At least a good part of what's described here is related to
it.
So, add it to the admin-guide.
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
Diffstat (limited to 'Documentation/admin-guide/perf/qcom_l2_pmu.rst')
-rw-r--r-- | Documentation/admin-guide/perf/qcom_l2_pmu.rst | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/Documentation/admin-guide/perf/qcom_l2_pmu.rst b/Documentation/admin-guide/perf/qcom_l2_pmu.rst new file mode 100644 index 000000000000..c130178a4a55 --- /dev/null +++ b/Documentation/admin-guide/perf/qcom_l2_pmu.rst @@ -0,0 +1,39 @@ +===================================================================== +Qualcomm Technologies Level-2 Cache Performance Monitoring Unit (PMU) +===================================================================== + +This driver supports the L2 cache clusters found in Qualcomm Technologies +Centriq SoCs. There are multiple physical L2 cache clusters, each with their +own PMU. Each cluster has one or more CPUs associated with it. + +There is one logical L2 PMU exposed, which aggregates the results from +the physical PMUs. + +The driver provides a description of its available events and configuration +options in sysfs, see /sys/devices/l2cache_0. + +The "format" directory describes the format of the events. + +Events can be envisioned as a 2-dimensional array. Each column represents +a group of events. There are 8 groups. Only one entry from each +group can be in use at a time. If multiple events from the same group +are specified, the conflicting events cannot be counted at the same time. + +Events are specified as 0xCCG, where CC is 2 hex digits specifying +the code (array row) and G specifies the group (column) 0-7. + +In addition there is a cycle counter event specified by the value 0xFE +which is outside the above scheme. + +The driver provides a "cpumask" sysfs attribute which contains a mask +consisting of one CPU per cluster which will be used to handle all the PMU +events on that cluster. + +Examples for use with perf:: + + perf stat -e l2cache_0/config=0x001/,l2cache_0/config=0x042/ -a sleep 1 + + perf stat -e l2cache_0/config=0xfe/ -C 2 sleep 1 + +The driver does not support sampling, therefore "perf record" will +not work. Per-task perf sessions are not supported. |