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author | Bjorn Helgaas <bhelgaas@google.com> | 2023-08-15 00:28:22 +0300 |
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committer | Jonathan Corbet <corbet@lwn.net> | 2023-08-18 20:29:03 +0300 |
commit | d56b699d76d1b352f7a3d3a0a3e91c79b8612d94 (patch) | |
tree | 2a368f3e2e17f7a516bf39e055f79d8c79a74885 /Documentation/arch/arm | |
parent | ebab9426cd73c45945b44344ca904b343f0ca070 (diff) | |
download | linux-d56b699d76d1b352f7a3d3a0a3e91c79b8612d94.tar.xz |
Documentation: Fix typos
Fix typos in Documentation.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/r/20230814212822.193684-4-helgaas@kernel.org
Signed-off-by: Jonathan Corbet <corbet@lwn.net>
Diffstat (limited to 'Documentation/arch/arm')
-rw-r--r-- | Documentation/arch/arm/arm.rst | 2 | ||||
-rw-r--r-- | Documentation/arch/arm/ixp4xx.rst | 4 | ||||
-rw-r--r-- | Documentation/arch/arm/sunxi/clocks.rst | 2 | ||||
-rw-r--r-- | Documentation/arch/arm/swp_emulation.rst | 2 | ||||
-rw-r--r-- | Documentation/arch/arm/tcm.rst | 2 | ||||
-rw-r--r-- | Documentation/arch/arm/vlocks.rst | 2 |
6 files changed, 7 insertions, 7 deletions
diff --git a/Documentation/arch/arm/arm.rst b/Documentation/arch/arm/arm.rst index 99d660fdf73f..7b41b89dd9bd 100644 --- a/Documentation/arch/arm/arm.rst +++ b/Documentation/arch/arm/arm.rst @@ -141,7 +141,7 @@ ST506 hard drives `*configure` harddrive set to 2). I've got an internal 20MB and a great big external 5.25" FH 64MB drive (who could ever want more :-) ). - I've just got 240K/s off it (a dd with bs=128k); thats about half of what + I've just got 240K/s off it (a dd with bs=128k); that's about half of what RiscOS gets; but it's a heck of a lot better than the 50K/s I was getting last week :-) diff --git a/Documentation/arch/arm/ixp4xx.rst b/Documentation/arch/arm/ixp4xx.rst index a57235616294..17aafc610908 100644 --- a/Documentation/arch/arm/ixp4xx.rst +++ b/Documentation/arch/arm/ixp4xx.rst @@ -78,9 +78,9 @@ IXP4xx provides two methods of accessing PCI memory space: 1) A direct mapped window from 0x48000000 to 0x4bffffff (64MB). To access PCI via this space, we simply ioremap() the BAR into the kernel and we can use the standard read[bwl]/write[bwl] - macros. This is the preffered method due to speed but it + macros. This is the preferred method due to speed but it limits the system to just 64MB of PCI memory. This can be - problamatic if using video cards and other memory-heavy devices. + problematic if using video cards and other memory-heavy devices. 2) If > 64MB of memory space is required, the IXP4xx can be configured to use indirect registers to access PCI This allows diff --git a/Documentation/arch/arm/sunxi/clocks.rst b/Documentation/arch/arm/sunxi/clocks.rst index 23bd03f3e21f..dfe6d4887210 100644 --- a/Documentation/arch/arm/sunxi/clocks.rst +++ b/Documentation/arch/arm/sunxi/clocks.rst @@ -5,7 +5,7 @@ Frequently asked questions about the sunxi clock system This document contains useful bits of information that people tend to ask about the sunxi clock system, as well as accompanying ASCII art when adequate. -Q: Why is the main 24MHz oscillator gatable? Wouldn't that break the +Q: Why is the main 24MHz oscillator gateable? Wouldn't that break the system? A: The 24MHz oscillator allows gating to save power. Indeed, if gated diff --git a/Documentation/arch/arm/swp_emulation.rst b/Documentation/arch/arm/swp_emulation.rst index 6a608a9c3715..bf205e3de36e 100644 --- a/Documentation/arch/arm/swp_emulation.rst +++ b/Documentation/arch/arm/swp_emulation.rst @@ -1,7 +1,7 @@ Software emulation of deprecated SWP instruction (CONFIG_SWP_EMULATE) --------------------------------------------------------------------- -ARMv6 architecture deprecates use of the SWP/SWPB instructions, and recommeds +ARMv6 architecture deprecates use of the SWP/SWPB instructions, and recommends moving to the load-locked/store-conditional instructions LDREX and STREX. ARMv7 multiprocessing extensions introduce the ability to disable these diff --git a/Documentation/arch/arm/tcm.rst b/Documentation/arch/arm/tcm.rst index 1dc6c39220f9..7ce17a248af9 100644 --- a/Documentation/arch/arm/tcm.rst +++ b/Documentation/arch/arm/tcm.rst @@ -71,7 +71,7 @@ in <asm/tcm.h>. Using this interface it is possible to: - Have the remaining TCM RAM added to a special allocation pool with gen_pool_create() and gen_pool_add() - and provice tcm_alloc() and tcm_free() for this + and provide tcm_alloc() and tcm_free() for this memory. Such a heap is great for things like saving device state when shutting off device power domains. diff --git a/Documentation/arch/arm/vlocks.rst b/Documentation/arch/arm/vlocks.rst index a40a1742110b..737aa8661a21 100644 --- a/Documentation/arch/arm/vlocks.rst +++ b/Documentation/arch/arm/vlocks.rst @@ -155,7 +155,7 @@ the basic algorithm: optimisation. If there are too many CPUs to read the currently_voting array in - one transaction then multiple transations are still required. The + one transaction then multiple transactions are still required. The implementation uses a simple loop of word-sized loads for this case. The number of transactions is still fewer than would be required if bytes were loaded individually. |