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authorSuzuki K Poulose <suzuki.poulose@arm.com>2017-03-14 21:13:25 +0300
committerCatalin Marinas <catalin.marinas@arm.com>2017-03-20 19:29:28 +0300
commitc8c3798d2369e4285da44b244638eafe446a8f8a (patch)
tree484cfb45948628e4945cd808d26efeb1021105e7 /Documentation/arm64
parent87da236ebc711644dcff2339ee5b854f1abf1fca (diff)
downloadlinux-c8c3798d2369e4285da44b244638eafe446a8f8a.tar.xz
arm64: v8.3: Support for Javascript conversion instruction
ARMv8.3 adds support for a new instruction to perform conversion from double precision floating point to integer to match the architected behaviour of the equivalent Javascript conversion. Expose the availability via HWCAP and MRS emulation. Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'Documentation/arm64')
-rw-r--r--Documentation/arm64/cpu-feature-registers.txt8
1 files changed, 8 insertions, 0 deletions
diff --git a/Documentation/arm64/cpu-feature-registers.txt b/Documentation/arm64/cpu-feature-registers.txt
index 61ca21ebef1a..5b279dcee9c6 100644
--- a/Documentation/arm64/cpu-feature-registers.txt
+++ b/Documentation/arm64/cpu-feature-registers.txt
@@ -169,6 +169,14 @@ infrastructure:
as available on the CPU where it is fetched and is not a system
wide safe value.
+ 4) ID_AA64ISAR1_EL1 - Instruction set attribute register 1
+
+ x--------------------------------------------------x
+ | Name | bits | visible |
+ |--------------------------------------------------|
+ | JSCVT | [15-12] | y |
+ x--------------------------------------------------x
+
Appendix I: Example
---------------------------