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authorJulien Grall <julien.grall@arm.com>2019-11-01 18:20:22 +0300
committerCatalin Marinas <catalin.marinas@arm.com>2019-11-01 18:53:55 +0300
commit478016c3839d53bd4c89af1f095195be543fa1a3 (patch)
treec2522c778abcc2d50362b43f25b46b041ccc29fe /Documentation/arm64
parenta8613e7070e771cea90d93eb1e8397246883065a (diff)
downloadlinux-478016c3839d53bd4c89af1f095195be543fa1a3.tar.xz
docs/arm64: cpu-feature-registers: Rewrite bitfields that don't follow [e, s]
Commit "docs/arm64: cpu-feature-registers: Documents missing visible fields" added bitfields following the convention [s, e]. However, the documentation is following [s, e] and so does the Arm ARM. Rewrite the bitfields to match the format [s, e]. Fixes: a8613e7070e7 ("docs/arm64: cpu-feature-registers: Documents missing visible fields") Signed-off-by: Julien Grall <julien.grall@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'Documentation/arm64')
-rw-r--r--Documentation/arm64/cpu-feature-registers.rst4
1 files changed, 2 insertions, 2 deletions
diff --git a/Documentation/arm64/cpu-feature-registers.rst b/Documentation/arm64/cpu-feature-registers.rst
index ffcf4e2c71ef..7c40e4581bae 100644
--- a/Documentation/arm64/cpu-feature-registers.rst
+++ b/Documentation/arm64/cpu-feature-registers.rst
@@ -193,9 +193,9 @@ infrastructure:
+------------------------------+---------+---------+
| Name | bits | visible |
+------------------------------+---------+---------+
- | SB | [36-39] | y |
+ | SB | [39-36] | y |
+------------------------------+---------+---------+
- | FRINTTS | [32-35] | y |
+ | FRINTTS | [35-32] | y |
+------------------------------+---------+---------+
| GPI | [31-28] | y |
+------------------------------+---------+---------+