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author | Masanari Iida <standby24x7@gmail.com> | 2017-01-05 17:43:07 +0300 |
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committer | Rob Herring <robh@kernel.org> | 2017-01-09 21:18:32 +0300 |
commit | 2956b338b729dcce90f9fa5e799df71908f09701 (patch) | |
tree | 61a773e725693200dceb1ff97a04300ce1442261 /Documentation/devicetree/bindings/bus | |
parent | 24f56ea66df78693cf588d00abf3cd22a4dec51d (diff) | |
download | linux-2956b338b729dcce90f9fa5e799df71908f09701.tar.xz |
bus:qcom : Fix typo in qcom,ebi2.txt
This patch fix 2 spelling typos found in qcom,ebi2.txt
Signed-off-by: Masanari Iida <standby24x7@gmail.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/bus')
-rw-r--r-- | Documentation/devicetree/bindings/bus/qcom,ebi2.txt | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/bus/qcom,ebi2.txt b/Documentation/devicetree/bindings/bus/qcom,ebi2.txt index 920681f552db..5a7d567f6833 100644 --- a/Documentation/devicetree/bindings/bus/qcom,ebi2.txt +++ b/Documentation/devicetree/bindings/bus/qcom,ebi2.txt @@ -51,7 +51,7 @@ Required properties: - compatible: should be one of: "qcom,msm8660-ebi2" "qcom,apq8060-ebi2" -- #address-cells: shoule be <2>: the first cell is the chipselect, +- #address-cells: should be <2>: the first cell is the chipselect, the second cell is the offset inside the memory range - #size-cells: should be <1> - ranges: should be set to: @@ -64,7 +64,7 @@ Required properties: - reg: two ranges of registers: EBI2 config and XMEM config areas - reg-names: should be "ebi2", "xmem" - clocks: two clocks, EBI_2X and EBI -- clock-names: shoule be "ebi2x", "ebi2" +- clock-names: should be "ebi2x", "ebi2" Optional subnodes: - Nodes inside the EBI2 will be considered device nodes. @@ -100,7 +100,7 @@ Optional properties arrays for FAST chip selects: assertion, with respect to the cycle where ADV (address valid) is asserted. 2 means 2 cycles between ADV and OE. Valid values 0, 1, 2 or 3. - qcom,xmem-read-hold-cycles: the length in cycles of the first segment of a - read transfer. For a single read trandfer this will be the time from CS + read transfer. For a single read transfer this will be the time from CS assertion to OE assertion. Valid values 0 thru 15. |