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author | Stephen Boyd <sboyd@kernel.org> | 2023-10-27 22:21:17 +0300 |
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committer | Stephen Boyd <sboyd@kernel.org> | 2023-10-27 22:21:17 +0300 |
commit | 0dea4e30fedad73ce3223b4d3d546fafc1aa77a6 (patch) | |
tree | 5a77c64169ea3e9b05d4e3210d18e0f3ca48e578 /Documentation/devicetree/bindings/clock/qcom,sm4450-gcc.yaml | |
parent | 0bb80ecc33a8fb5a682236443c1e740d5c917d1d (diff) | |
parent | e0e6373d653b7707bf042ecf1538884597c5d0da (diff) | |
download | linux-0dea4e30fedad73ce3223b4d3d546fafc1aa77a6.tar.xz |
Merge tag 'qcom-clk-for-6.7' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom
Pull Qualcomm clk driver updates from Bjorn Andersson:
- Initial support for the SM4450 Global Clock Controller and RPMh clock controllers
- Drop CLK_SET_RATE_PARENT for clocks with fixed-rate GPLLs across a variety of IPQ platforms
- Add missing parent of APCS PLL on IPQ6018
- Add I2C QUP6 clk on IPQ6018 but mark it critical to avoid problems with RPM
- Implement safe source switching for a53pll and use on IPQ5332
- Add support for Stromer Plus PLLs
- Switch SM8550 Video and GPU clock controllers to use OLE PLL configure method
- Non critical fixes to halt bit checks
- Add SMMU GDSC for MSM8998
- Fix possible integer overflow in RCG frequency calculation code
- Remove RPM managed clks from MSM8996 GCC driver
- Add Camera Clock Controller on SM8550
- Add HFPLL configuration for the three HFPLLs in MSM8976
- Switch MSM8996 CBF clock driver's remove function to return void
* tag 'qcom-clk-for-6.7' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (36 commits)
clk: qcom: apss-ipq6018: add the GPLL0 clock also as clock provider
clk: qcom: ipq5332: drop the CLK_SET_RATE_PARENT flag from GPLL clocks
clk: qcom: ipq9574: drop the CLK_SET_RATE_PARENT flag from GPLL clocks
clk: qcom: ipq5018: drop the CLK_SET_RATE_PARENT flag from GPLL clocks
clk: qcom: ipq6018: drop the CLK_SET_RATE_PARENT flag from PLL clocks
clk: qcom: ipq8074: drop the CLK_SET_RATE_PARENT flag from PLL clocks
clk: qcom: gcc-ipq6018: add QUP6 I2C clock
clk: qcom: apss-ipq6018: ipq5332: add safe source switch for a53pll
clk: qcom: apss-ipq-pll: Fix 'l' value for ipq5332_pll_config
clk: qcom: apss-ipq-pll: Use stromer plus ops for stromer plus pll
clk: qcom: clk-alpha-pll: introduce stromer plus ops
clk: qcom: config IPQ_APSS_6018 should depend on QCOM_SMEM
clk: qcom: videocc-sm8550: switch to clk_lucid_ole_pll_configure
clk: qcom: gpucc-sm8550: switch to clk_lucid_ole_pll_configure
clk: qcom: Replace of_device.h with explicit includes
clk: qcom: smd-rpm: Move CPUSS_GNoC clock to interconnect
clk: qcom: cbf-msm8996: Convert to platform remove callback returning void
clk: qcom: gcc-sm8150: Fix gcc_sdcc2_apps_clk_src
clk: qcom: Add GCC driver support for SM4450
dt-bindings: clock: qcom: Add GCC clocks for SM4450
...
Diffstat (limited to 'Documentation/devicetree/bindings/clock/qcom,sm4450-gcc.yaml')
-rw-r--r-- | Documentation/devicetree/bindings/clock/qcom,sm4450-gcc.yaml | 55 |
1 files changed, 55 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/qcom,sm4450-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm4450-gcc.yaml new file mode 100644 index 000000000000..5953c8d92436 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm4450-gcc.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm4450-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on SM4450 + +maintainers: + - Ajit Pandey <quic_ajipan@quicinc.com> + - Taniya Das <quic_tdas@quicinc.com> + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on SM4450 + + See also:: include/dt-bindings/clock/qcom,sm4450-gcc.h + +properties: + compatible: + const: qcom,sm4450-gcc + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + - description: UFS Phy Rx symbol 0 clock source + - description: UFS Phy Rx symbol 1 clock source + - description: UFS Phy Tx symbol 0 clock source + - description: USB3 Phy wrapper pipe clock source + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + clock-controller@100000 { + compatible = "qcom,sm4450-gcc"; + reg = <0x00100000 0x001f4200>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, + <&ufs_mem_phy 0>, <&ufs_mem_phy 1>, + <&ufs_mem_phy 2>, <&usb_1_qmpphy>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + +... |