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| author | Srinivas Kandagatla <srinivas.kandagatla@linaro.org> | 2024-06-24 16:32:37 +0300 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2024-08-15 22:14:54 +0300 |
| commit | 386e0ac929f64de4c9df33e247d5acd514cd1c58 (patch) | |
| tree | a8e266da60a66dd022c77cbd3042123bb397a307 /Documentation/devicetree/bindings/clock | |
| parent | 6319bdd24e4b29d82496c103ed6606e1a470bc13 (diff) | |
| download | linux-386e0ac929f64de4c9df33e247d5acd514cd1c58.tar.xz | |
dt-bindings: clock: Add x1e80100 LPASSCC reset controller
X1E80100 LPASS (Low Power Audio Subsystem) clock controller provides reset
support when it is under the control of Q6DSP.
Add x1e80100 compatible to the existing sc8280xp as these reset
controllers have same reg layout and compatible.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240624-x1e-swr-reset-v2-2-8bc677fcfa64@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/clock')
| -rw-r--r-- | Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml index c33bf4c5af7d..273d66e245c5 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml @@ -25,6 +25,10 @@ properties: - items: - const: qcom,x1e80100-lpassaudiocc - const: qcom,sc8280xp-lpassaudiocc + - items: + - const: qcom,x1e80100-lpasscc + - const: qcom,sc8280xp-lpasscc + reg: maxItems: 1 |