diff options
author | Stefan M Schaeckeler <sschaeck@cisco.com> | 2019-01-17 19:38:17 +0300 |
---|---|---|
committer | Borislav Petkov <bp@suse.de> | 2019-01-18 17:26:49 +0300 |
commit | 5296bab33b6037897a1e32958ddbc2b3dab405be (patch) | |
tree | 3af1ed438c422d24327fd9c9d27239853ec1c9bf /Documentation/devicetree/bindings/edac | |
parent | 9b7e6242ee4efcd7f9ef699bf1965e3a5343f216 (diff) | |
download | linux-5296bab33b6037897a1e32958ddbc2b3dab405be.tar.xz |
dt-bindings, EDAC: Add Aspeed AST2500
Add support for EDAC on the Aspeed AST2500 SoC.
Signed-off-by: Stefan M Schaeckeler <sschaeck@cisco.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Cc: Joel Stanley <joel@jms.id.au>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mauro Carvalho Chehab <mchehab@kernel.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-aspeed@lists.ozlabs.org
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: https://lkml.kernel.org/r/1547743097-5236-3-git-send-email-schaecsn@gmx.net
Diffstat (limited to 'Documentation/devicetree/bindings/edac')
-rw-r--r-- | Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt b/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt new file mode 100644 index 000000000000..6a0f3d90d682 --- /dev/null +++ b/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt @@ -0,0 +1,25 @@ +Aspeed AST2500 SoC EDAC node + +The Aspeed AST2500 SoC supports DDR3 and DDR4 memory with and without ECC (error +correction check). + +The memory controller supports SECDED (single bit error correction, double bit +error detection) and single bit error auto scrubbing by reserving 8 bits for +every 64 bit word (effectively reducing available memory to 8/9). + +Note, the bootloader must configure ECC mode in the memory controller. + + +Required properties: +- compatible: should be "aspeed,ast2500-sdram-edac" +- reg: sdram controller register set should be <0x1e6e0000 0x174> +- interrupts: should be AVIC interrupt #0 + + +Example: + + edac: sdram@1e6e0000 { + compatible = "aspeed,ast2500-sdram-edac"; + reg = <0x1e6e0000 0x174>; + interrupts = <0>; + }; |