diff options
author | Linus Walleij <linus.walleij@linaro.org> | 2019-02-11 00:40:48 +0300 |
---|---|---|
committer | Linus Walleij <linus.walleij@linaro.org> | 2019-04-23 17:02:16 +0300 |
commit | 3107fbf7059bcad924a241271f667dc2f74910a5 (patch) | |
tree | 993291c66f19f07279a95513a8765436dacb1ecb /Documentation/devicetree/bindings/firmware | |
parent | ecc133c6da60377c54a117841d630612d9f49964 (diff) | |
download | linux-3107fbf7059bcad924a241271f667dc2f74910a5.tar.xz |
soc: ixp4xx: Add DT bindings for IXP4xx NPE
This adds DT bindings for the Intel IXP4xx Network Processing
Engine (NPE). These are three firmware-executing units found in
the IXP4xx SoC. These bindings use YAML.
Cc: devicetree@vger.kernel.org
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'Documentation/devicetree/bindings/firmware')
-rw-r--r-- | Documentation/devicetree/bindings/firmware/intel,ixp4xx-network-processing-engine.yaml | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/firmware/intel,ixp4xx-network-processing-engine.yaml b/Documentation/devicetree/bindings/firmware/intel,ixp4xx-network-processing-engine.yaml new file mode 100644 index 000000000000..8cb136c376fb --- /dev/null +++ b/Documentation/devicetree/bindings/firmware/intel,ixp4xx-network-processing-engine.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2019 Linaro Ltd. +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/firmware/intel-ixp4xx-network-processing-engine.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Intel IXP4xx Network Processing Engine + +maintainers: + - Linus Walleij <linus.walleij@linaro.org> + +description: | + On the IXP4xx SoCs, the Network Processing Engine (NPE) is a small + processor that can load a firmware to perform offloading of networking + and crypto tasks. It also manages the MDIO bus to the ethernet PHYs + on the IXP4xx platform. All IXP4xx platforms have three NPEs at + consecutive memory locations. They are all included in the same + device node since they are not independent of each other. + +properties: + compatible: + oneOf: + - items: + - const: intel,ixp4xx-network-processing-engine + + reg: + minItems: 3 + maxItems: 3 + items: + - description: NPE0 register range + - description: NPE1 register range + - description: NPE2 register range + +required: + - compatible + - reg + +examples: + - | + npe@c8006000 { + compatible = "intel,ixp4xx-network-processing-engine"; + reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>; + }; |