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authorRichard Gong <richard.gong@intel.com>2018-11-13 21:13:59 +0300
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2018-11-26 22:13:50 +0300
commita2c1c192656b701939b9028646b8a8bb90edd911 (patch)
tree91e6a7910dacdd82e9239ed8503433af069f2297 /Documentation/devicetree/bindings/firmware
parent1a195d87d2c58aa9524af9531539ccfa203cd52c (diff)
downloadlinux-a2c1c192656b701939b9028646b8a8bb90edd911.tar.xz
dt-bindings, firmware: add Intel Stratix10 service layer binding
Add a device tree binding for the Intel Stratix10 service layer driver Signed-off-by: Richard Gong <richard.gong@intel.com> Signed-off-by: Alan Tull <atull@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Moritz Fischer <mdf@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'Documentation/devicetree/bindings/firmware')
-rw-r--r--Documentation/devicetree/bindings/firmware/intel,stratix10-svc.txt57
1 files changed, 57 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.txt b/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.txt
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index 000000000000..1fa66065acc6
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+++ b/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.txt
@@ -0,0 +1,57 @@
+Intel Service Layer Driver for Stratix10 SoC
+============================================
+Intel Stratix10 SoC is composed of a 64 bit quad-core ARM Cortex A53 hard
+processor system (HPS) and Secure Device Manager (SDM). When the FPGA is
+configured from HPS, there needs to be a way for HPS to notify SDM the
+location and size of the configuration data. Then SDM will get the
+configuration data from that location and perform the FPGA configuration.
+
+To meet the whole system security needs and support virtual machine requesting
+communication with SDM, only the secure world of software (EL3, Exception
+Layer 3) can interface with SDM. All software entities running on other
+exception layers must channel through the EL3 software whenever it needs
+service from SDM.
+
+Intel Stratix10 service layer driver, running at privileged exception level
+(EL1, Exception Layer 1), interfaces with the service providers and provides
+the services for FPGA configuration, QSPI, Crypto and warm reset. Service layer
+driver also manages secure monitor call (SMC) to communicate with secure monitor
+code running in EL3.
+
+Required properties:
+-------------------
+The svc node has the following mandatory properties, must be located under
+the firmware node.
+
+- compatible: "intel,stratix10-svc"
+- method: smc or hvc
+ smc - Secure Monitor Call
+ hvc - Hypervisor Call
+- memory-region:
+ phandle to the reserved memory node. See
+ Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
+ for details
+
+Example:
+-------
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ service_reserved: svcbuffer@0 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x0 0x0 0x1000000>;
+ alignment = <0x1000>;
+ no-map;
+ };
+ };
+
+ firmware {
+ svc {
+ compatible = "intel,stratix10-svc";
+ method = "smc";
+ memory-region = <&service_reserved>;
+ };
+ };