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author | Joel Stanley <joel@jms.id.au> | 2019-04-03 03:19:07 +0300 |
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committer | Joel Stanley <joel@jms.id.au> | 2019-04-04 04:06:26 +0300 |
commit | eff9f244c1237f681c41dd66b811efec590e9deb (patch) | |
tree | 21e25ff553a5a8e86e4a0ec9b2cce72c61d003c3 /Documentation/devicetree/bindings/gpu | |
parent | ffc26740714962e3e8801dca7ef32b636b3781db (diff) | |
download | linux-eff9f244c1237f681c41dd66b811efec590e9deb.tar.xz |
dt-bindings: gpu: Add ASPEED GFX bindings document
This describes the ASPEED BMC SoC's display controller.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://patchwork.freedesktop.org/patch/msgid/20190403001909.31637-2-joel@jms.id.au
Diffstat (limited to 'Documentation/devicetree/bindings/gpu')
-rw-r--r-- | Documentation/devicetree/bindings/gpu/aspeed-gfx.txt | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/gpu/aspeed-gfx.txt b/Documentation/devicetree/bindings/gpu/aspeed-gfx.txt new file mode 100644 index 000000000000..958bdf962339 --- /dev/null +++ b/Documentation/devicetree/bindings/gpu/aspeed-gfx.txt @@ -0,0 +1,41 @@ +Device tree configuration for the GFX display device on the ASPEED SoCs + +Required properties: + - compatible + * Must be one of the following: + + aspeed,ast2500-gfx + + aspeed,ast2400-gfx + * In addition, the ASPEED pinctrl bindings require the 'syscon' property to + be present + + - reg: Physical base address and length of the GFX registers + + - interrupts: interrupt number for the GFX device + + - clocks: clock number used to generate the pixel clock + + - resets: reset line that must be released to use the GFX device + + - memory-region: + Phandle to a memory region to allocate from, as defined in + Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt + + +Example: + +gfx: display@1e6e6000 { + compatible = "aspeed,ast2500-gfx", "syscon"; + reg = <0x1e6e6000 0x1000>; + reg-io-width = <4>; + clocks = <&syscon ASPEED_CLK_GATE_D1CLK>; + resets = <&syscon ASPEED_RESET_CRT1>; + interrupts = <0x19>; + memory-region = <&gfx_memory>; +}; + +gfx_memory: framebuffer { + size = <0x01000000>; + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; +}; |