diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2023-04-27 19:23:57 +0300 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2023-04-27 19:23:57 +0300 |
commit | d42b1c47570eb2ed818dc3fe94b2678124af109d (patch) | |
tree | b95a1ab93d7ea3e02a17532489aa1297a19aadfc /Documentation/devicetree/bindings/interrupt-controller | |
parent | 6df969b77ecc2ba21dcd0e57f416e58bec2a5ca1 (diff) | |
parent | 66ae0535167660e427f9fcadeee5d05646e2bb22 (diff) | |
download | linux-d42b1c47570eb2ed818dc3fe94b2678124af109d.tar.xz |
Merge tag 'devicetree-for-6.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull devicetree updates from Rob Herring:
"Bindings:
- Convert Qcom IOMMU, Amlogic timer, Freescale sec-v4.0, Toshiba
TC358764 display bridge, Parade PS8622 display bridge, and Xilinx
FPGA bindings to DT schema format
- Add qdu1000 and sa8775p SoC support to Qcom PDC interrupt
controller
- Add MediaTek MT8365 UART and SYSIRQ bindings
- Add Arm Cortex-A78C and X1C core compatibles
- Add vendor prefix for Novatek
- Remove bindings for stih415, sti416, stid127 platforms
- Drop uneeded quotes in schema files. This is preparation for
yamllint checking quoting for us.
- Add missing (unevaluated|additional)Properties constraints on child
node schemas
- Clean-up schema comments formatting
- Fix I2C and SPI node bus names in schema examples
- Clean-up some display compatibles schema syntax
- Fix incorrect references to lvds.yaml
- Gather all cache controller bindings in a common directory
DT core:
- Convert unittest to new void .remove platform device hook
- kerneldoc fixes for DT address of_pci_range_to_resource/
of_address_to_resource functions"
* tag 'devicetree-for-6.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (46 commits)
dt-bindings: rng: Drop unneeded quotes
dt-bindings: arm/soc: mediatek: Drop unneeded quotes
dt-bindings: soc: qcom: Drop unneeded quotes
dt-bindings: i2c: samsung: Fix 'deprecated' value
dt-bindings: display: Fix lvds.yaml references
dt-bindings: display: simplify compatibles syntax
dt-bindings: display: mediatek: simplify compatibles syntax
dt-bindings: drm/bridge: ti-sn65dsi86: Fix the video-interfaces.yaml references
dt-bindings: timer: Drop unneeded quotes
dt-bindings: interrupt-controller: qcom,pdc: document qcom,qdu1000-pdc
dt-bindings: interrupt-controller: qcom-pdc: add compatible for sa8775p
dt-bindings: reset: remove stih415/stih416 reset
dt-bindings: net: dwmac: sti: remove stih415/sti416/stid127
dt-bindings: irqchip: sti: remove stih415/stih416 and stid127
dt-bindings: iommu: Convert QCOM IOMMU to YAML
dt-bindings: irqchip: ti,sci-inta: Add optional power-domains property
dt-bindings: Add missing (unevaluated|additional)Properties on child node schemas
of: address: Reshuffle to remove forward declarations
of: address: Fix documented return value of of_pci_range_to_resource()
of: address: Document return value of of_address_to_resource()
...
Diffstat (limited to 'Documentation/devicetree/bindings/interrupt-controller')
19 files changed, 44 insertions, 41 deletions
diff --git a/Documentation/devicetree/bindings/interrupt-controller/actions,owl-sirq.yaml b/Documentation/devicetree/bindings/interrupt-controller/actions,owl-sirq.yaml index 5da333c644c9..27756d0c5419 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/actions,owl-sirq.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/actions,owl-sirq.yaml @@ -32,7 +32,7 @@ properties: The first cell is the input IRQ number, between 0 and 2, while the second cell is the trigger type as defined in interrupt.txt in this directory. - 'interrupts': + interrupts: description: | Contains the GIC SPI IRQs mapped to the external interrupt lines. They shall be specified sequentially from output 0 to 2. @@ -44,7 +44,7 @@ required: - reg - interrupt-controller - '#interrupt-cells' - - 'interrupts' + - interrupts additionalProperties: false diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml index 8449e14af9f3..92117261e1e1 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml @@ -133,12 +133,14 @@ properties: ppi-partitions: type: object + additionalProperties: false description: PPI affinity can be expressed as a single "ppi-partitions" node, containing a set of sub-nodes. patternProperties: "^interrupt-partition-[0-9]+$": type: object + additionalProperties: false properties: affinity: $ref: /schemas/types.yaml#/definitions/phandle-array diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml index 220256907461..a2846e493497 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml @@ -133,8 +133,8 @@ properties: - items: # for "arm,cortex-a9-gic" - const: PERIPHCLK - const: PERIPHCLKEN - - const: clk # for "arm,gic-400" and "nvidia,tegra210" - - const: gclk #for "arm,pl390" + - const: clk # for "arm,gic-400" and "nvidia,tegra210" + - const: gclk # for "arm,pl390" power-domains: maxItems: 1 diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml b/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml index bcb5e20fa9ca..20ad4ad82ad6 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml @@ -48,13 +48,13 @@ properties: const: 1 fsl,channel: - $ref: '/schemas/types.yaml#/definitions/uint32' + $ref: /schemas/types.yaml#/definitions/uint32 description: | u32 value representing the output channel that all input IRQs should be steered into. fsl,num-irqs: - $ref: '/schemas/types.yaml#/definitions/uint32' + $ref: /schemas/types.yaml#/definitions/uint32 description: | u32 value representing the number of input interrupts of this channel, should be multiple of 32 input interrupts and up to 512 interrupts. diff --git a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.yaml b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.yaml index 39ab8cdd19b4..a3ac818f067d 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-ioapic.yaml @@ -1,8 +1,8 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/interrupt-controller/intel,ce4100-ioapic.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/interrupt-controller/intel,ce4100-ioapic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Intel I/O Advanced Programmable Interrupt Controller (IO APIC) diff --git a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml index d2d0145cb889..6b20a5fa8590 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-lapic.yaml @@ -1,8 +1,8 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/interrupt-controller/intel,ce4100-lapic.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/interrupt-controller/intel,ce4100-lapic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Intel Local Advanced Programmable Interrupt Controller (LAPIC) diff --git a/Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml b/Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml index 14dced11877b..a02a6b5af205 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml @@ -2,8 +2,8 @@ # Copyright 2018 Linaro Ltd. %YAML 1.2 --- -$id: "http://devicetree.org/schemas/interrupt-controller/intel,ixp4xx-interrupt.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/interrupt-controller/intel,ixp4xx-interrupt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Intel IXP4xx XScale Networking Processors Interrupt Controller diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongson,htpic.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongson,htpic.yaml index d6bc1a687fc7..f0acd5671bb1 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/loongson,htpic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,htpic.yaml @@ -1,8 +1,8 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/interrupt-controller/loongson,htpic.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/interrupt-controller/loongson,htpic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Loongson-3 HyperTransport Interrupt Controller diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongson,htvec.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongson,htvec.yaml index 87a74558204f..1d145763908e 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/loongson,htvec.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,htvec.yaml @@ -1,8 +1,8 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/interrupt-controller/loongson,htvec.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/interrupt-controller/loongson,htvec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Loongson-3 HyperTransport Interrupt Vector Controller diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml index 750cc44628e9..00b570c82903 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml @@ -1,8 +1,8 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/interrupt-controller/loongson,liointc.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/interrupt-controller/loongson,liointc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Loongson Local I/O Interrupt Controller @@ -54,7 +54,7 @@ properties: '#interrupt-cells': const: 2 - 'loongson,parent_int_map': + loongson,parent_int_map: description: | This property points how the children interrupts will be mapped into CPU interrupt lines. Each cell refers to a parent interrupt line from 0 to 3 @@ -71,7 +71,7 @@ required: - interrupts - interrupt-controller - '#interrupt-cells' - - 'loongson,parent_int_map' + - loongson,parent_int_map unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongson,pch-msi.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongson,pch-msi.yaml index 1f6fd73d4624..a71fc2218ede 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/loongson,pch-msi.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,pch-msi.yaml @@ -1,8 +1,8 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/interrupt-controller/loongson,pch-msi.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/interrupt-controller/loongson,pch-msi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Loongson PCH MSI Controller @@ -25,7 +25,7 @@ properties: description: u32 value of the base of parent HyperTransport vector allocated to PCH MSI. - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 255 @@ -33,7 +33,7 @@ properties: description: u32 value of the number of parent HyperTransport vectors allocated to PCH MSI. - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 minimum: 1 maximum: 256 @@ -46,7 +46,7 @@ required: - loongson,msi-base-vec - loongson,msi-num-vecs -additionalProperties: true #fixme +additionalProperties: true # fixme examples: - | diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongson,pch-pic.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongson,pch-pic.yaml index fdd6a38a31db..b7bc5cb1dff2 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/loongson,pch-pic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,pch-pic.yaml @@ -1,8 +1,8 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/interrupt-controller/loongson,pch-pic.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/interrupt-controller/loongson,pch-pic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Loongson PCH PIC Controller @@ -25,7 +25,7 @@ properties: description: u32 value of the base of parent HyperTransport vector allocated to PCH PIC. - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 192 diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt index 84ced3f4179b..3ffc60184e44 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt @@ -25,6 +25,7 @@ Required properties: "mediatek,mt6577-sysirq": for MT6577 "mediatek,mt2712-sysirq", "mediatek,mt6577-sysirq": for MT2712 "mediatek,mt2701-sysirq", "mediatek,mt6577-sysirq": for MT2701 + "mediatek,mt8365-sysirq", "mediatek,mt6577-sysirq": for MT8365 - interrupt-controller : Identifies the node as an interrupt controller - #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt. - reg: Physical base address of the intpol registers and length of memory diff --git a/Documentation/devicetree/bindings/interrupt-controller/mrvl,intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/mrvl,intc.yaml index 9acc21028413..b7c5022eec84 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/mrvl,intc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/mrvl,intc.yaml @@ -53,8 +53,8 @@ allOf: maxItems: 1 reg-names: items: - - const: 'mux status' - - const: 'mux mask' + - const: mux status + - const: mux mask required: - interrupts else: diff --git a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml index 27b798bfe29b..4ff609faba32 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml @@ -1,8 +1,8 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/interrupt-controller/mscc,ocelot-icpu-intr.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/interrupt-controller/mscc,ocelot-icpu-intr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Microsemi Ocelot SoC ICPU Interrupt Controller diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml index 94791e261c42..a106ba6e810b 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml @@ -26,6 +26,8 @@ properties: compatible: items: - enum: + - qcom,qdu1000-pdc + - qcom,sa8775p-pdc - qcom,sc7180-pdc - qcom,sc7280-pdc - qcom,sc8280xp-pdc @@ -53,7 +55,7 @@ properties: qcom,pdc-ranges: $ref: /schemas/types.yaml#/definitions/uint32-matrix minItems: 1 - maxItems: 32 # no hard limit + maxItems: 128 # no hard limit items: items: - description: starting PDC port diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml index 4e98261f2948..f75736a061af 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -91,7 +91,7 @@ properties: riscv,cpu-intc node, which has a riscv node as parent. riscv,ndev: - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 description: Specifies how many external interrupts are supported by this controller. diff --git a/Documentation/devicetree/bindings/interrupt-controller/st,sti-irq-syscfg.txt b/Documentation/devicetree/bindings/interrupt-controller/st,sti-irq-syscfg.txt index ced6014061a3..977d7ed3670e 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/st,sti-irq-syscfg.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/st,sti-irq-syscfg.txt @@ -6,11 +6,7 @@ and PL310 L2 Cache IRQs are controlled using System Configuration registers. This driver is used to unmask them prior to use. Required properties: -- compatible : Should be set to one of: - "st,stih415-irq-syscfg" - "st,stih416-irq-syscfg" - "st,stih407-irq-syscfg" - "st,stid127-irq-syscfg" +- compatible : Should be "st,stih407-irq-syscfg" - st,syscfg : Phandle to Cortex-A9 IRQ system config registers - st,irq-device : Array of IRQs to enable - should be 2 in length - st,fiq-device : Array of FIQs to enable - should be 2 in length @@ -25,11 +21,10 @@ Optional properties: Example: irq-syscfg { - compatible = "st,stih416-irq-syscfg"; + compatible = "st,stih407-irq-syscfg"; st,syscfg = <&syscfg_cpu>; st,irq-device = <ST_IRQ_SYSCFG_PMU_0>, <ST_IRQ_SYSCFG_PMU_1>; st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>, <ST_IRQ_SYSCFG_DISABLED>; - st,invert-ext = <(ST_IRQ_SYSCFG_EXT_1_INV | ST_IRQ_SYSCFG_EXT_3_INV)>; }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,sci-inta.yaml b/Documentation/devicetree/bindings/interrupt-controller/ti,sci-inta.yaml index 1151518859bd..6a49d74b992a 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/ti,sci-inta.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/ti,sci-inta.yaml @@ -85,6 +85,9 @@ properties: description: Array of phandles to DMA controllers where the unmapped events originate. + power-domains: + maxItems: 1 + required: - compatible - reg |