diff options
author | Krzysztof Kozlowski <krzk@kernel.org> | 2019-09-18 20:31:37 +0300 |
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committer | Rob Herring <robh@kernel.org> | 2019-10-11 00:23:39 +0300 |
commit | a2c02a4304eb6588b72522308db1208438880d0e (patch) | |
tree | 3051e22c09a9c6896a2eac85b733bdc24eebd1f7 /Documentation/devicetree/bindings/memory-controllers | |
parent | 73b2608a28afe58b5387697429f29d5c5499f7c4 (diff) | |
download | linux-a2c02a4304eb6588b72522308db1208438880d0e.tar.xz |
dt-bindings: memory-controllers: Convert Samsung Exynos SROM bindings to json-schema
Convert Samsung Exynos SROM controller bindings to DT schema format
using json-schema.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/memory-controllers')
-rw-r--r-- | Documentation/devicetree/bindings/memory-controllers/exynos-srom.txt | 79 | ||||
-rw-r--r-- | Documentation/devicetree/bindings/memory-controllers/exynos-srom.yaml | 128 |
2 files changed, 128 insertions, 79 deletions
diff --git a/Documentation/devicetree/bindings/memory-controllers/exynos-srom.txt b/Documentation/devicetree/bindings/memory-controllers/exynos-srom.txt deleted file mode 100644 index f633b5d0f8ca..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/exynos-srom.txt +++ /dev/null @@ -1,79 +0,0 @@ -SAMSUNG Exynos SoCs SROM Controller driver. - -Required properties: -- compatible : Should contain "samsung,exynos4210-srom". - -- reg: offset and length of the register set - -Optional properties: -The SROM controller can be used to attach external peripherals. In this case -extra properties, describing the bus behind it, should be specified as below: - -- #address-cells: Must be set to 2 to allow device address translation. - Address is specified as (bank#, offset). - -- #size-cells: Must be set to 1 to allow device size passing - -- ranges: Must be set up to reflect the memory layout with four integer values - per bank: - <bank-number> 0 <parent address of bank> <size> - -Sub-nodes: -The actual device nodes should be added as subnodes to the SROMc node. These -subnodes, in addition to regular device specification, should contain the following -properties, describing configuration of the relevant SROM bank: - -Required properties: -- reg: bank number, base address (relative to start of the bank) and size of - the memory mapped for the device. Note that base address will be - typically 0 as this is the start of the bank. - -- samsung,srom-timing : array of 6 integers, specifying bank timings in the - following order: Tacp, Tcah, Tcoh, Tacc, Tcos, Tacs. - Each value is specified in cycles and has the following - meaning and valid range: - Tacp : Page mode access cycle at Page mode (0 - 15) - Tcah : Address holding time after CSn (0 - 15) - Tcoh : Chip selection hold on OEn (0 - 15) - Tacc : Access cycle (0 - 31, the actual time is N + 1) - Tcos : Chip selection set-up before OEn (0 - 15) - Tacs : Address set-up before CSn (0 - 15) - -Optional properties: -- reg-io-width : data width in bytes (1 or 2). If omitted, default of 1 is used. - -- samsung,srom-page-mode : if page mode is set, 4 data page mode will be configured, - else normal (1 data) page mode will be set. - -Example: basic definition, no banks are configured - memory-controller@12570000 { - compatible = "samsung,exynos4210-srom"; - reg = <0x12570000 0x14>; - }; - -Example: SROMc with SMSC911x ethernet chip on bank 3 - memory-controller@12570000 { - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0x04000000 0x20000 // Bank0 - 1 0 0x05000000 0x20000 // Bank1 - 2 0 0x06000000 0x20000 // Bank2 - 3 0 0x07000000 0x20000>; // Bank3 - - compatible = "samsung,exynos4210-srom"; - reg = <0x12570000 0x14>; - - ethernet@3,0 { - compatible = "smsc,lan9115"; - reg = <3 0 0x10000>; // Bank 3, offset = 0 - phy-mode = "mii"; - interrupt-parent = <&gpx0>; - interrupts = <5 8>; - reg-io-width = <2>; - smsc,irq-push-pull; - smsc,force-internal-phy; - - samsung,srom-page-mode; - samsung,srom-timing = <9 12 1 9 1 1>; - }; - }; diff --git a/Documentation/devicetree/bindings/memory-controllers/exynos-srom.yaml b/Documentation/devicetree/bindings/memory-controllers/exynos-srom.yaml new file mode 100644 index 000000000000..cdfe3f7f0ea9 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/exynos-srom.yaml @@ -0,0 +1,128 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/exynos-srom.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos SoC SROM Controller driver + +maintainers: + - Krzysztof Kozlowski <krzk@kernel.org> + +description: |+ + The SROM controller can be used to attach external peripherals. In this case + extra properties, describing the bus behind it, should be specified. + +properties: + compatible: + items: + - const: samsung,exynos4210-srom + + reg: + maxItems: 1 + + "#address-cells": + const: 2 + + "#size-cells": + const: 1 + + ranges: + description: | + Reflects the memory layout with four integer values per bank. Format: + <bank-number> 0 <parent address of bank> <size> + Up to four banks are supported. + +patternProperties: + "^.*@[0-3],[a-f0-9]+$": + type: object + description: + The actual device nodes should be added as subnodes to the SROMc node. + These subnodes, in addition to regular device specification, should + contain the following properties, describing configuration + of the relevant SROM bank. + + properties: + reg: + description: + Bank number, base address (relative to start of the bank) and size + of the memory mapped for the device. Note that base address will be + typically 0 as this is the start of the bank. + maxItems: 1 + + reg-io-width: + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [1, 2] + description: + Data width in bytes (1 or 2). If omitted, default of 1 is used. + + samsung,srom-page-mode: + description: + If page mode is set, 4 data page mode will be configured, + else normal (1 data) page mode will be set. + type: boolean + + samsung,srom-timing: + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32-array + - items: + minItems: 6 + maxItems: 6 + description: | + Array of 6 integers, specifying bank timings in the following order: + Tacp, Tcah, Tcoh, Tacc, Tcos, Tacs. + Each value is specified in cycles and has the following meaning + and valid range: + Tacp: Page mode access cycle at Page mode (0 - 15) + Tcah: Address holding time after CSn (0 - 15) + Tcoh: Chip selection hold on OEn (0 - 15) + Tacc: Access cycle (0 - 31, the actual time is N + 1) + Tcos: Chip selection set-up before OEn (0 - 15) + Tacs: Address set-up before CSn (0 - 15) + + required: + - reg + - samsung,srom-timing + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + // Example: basic definition, no banks are configured + memory-controller@12560000 { + compatible = "samsung,exynos4210-srom"; + reg = <0x12560000 0x14>; + }; + + - | + // Example: SROMc with SMSC911x ethernet chip on bank 3 + memory-controller@12570000 { + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x04000000 0x20000 // Bank0 + 1 0 0x05000000 0x20000 // Bank1 + 2 0 0x06000000 0x20000 // Bank2 + 3 0 0x07000000 0x20000>; // Bank3 + + compatible = "samsung,exynos4210-srom"; + reg = <0x12570000 0x14>; + + ethernet@3,0 { + compatible = "smsc,lan9115"; + reg = <3 0 0x10000>; // Bank 3, offset = 0 + phy-mode = "mii"; + interrupt-parent = <&gpx0>; + interrupts = <5 8>; + reg-io-width = <2>; + smsc,irq-push-pull; + smsc,force-internal-phy; + + samsung,srom-page-mode; + samsung,srom-timing = <9 12 1 9 1 1>; + }; + }; |