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authorArnd Bergmann <arnd@arndb.de>2017-12-21 19:52:50 +0300
committerArnd Bergmann <arnd@arndb.de>2017-12-21 19:52:50 +0300
commit30e18df6d32c76365bea6b1cd6309def8dbcc6b3 (patch)
treec374383a51c8a3fd93bcba2b1032a595873b827c /Documentation/devicetree/bindings/misc
parentce63eb7dc460adfbfc8c7a809b8fb6d45a3d0ad4 (diff)
parent029ab5eaf091ce5eaa1f3017f66fd1d10f431d61 (diff)
downloadlinux-30e18df6d32c76365bea6b1cd6309def8dbcc6b3.tar.xz
Merge tag 'tegra-for-4.16-dt-bindings' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt
Pull "dt-bindings: Updates for v4.16-rc1" from Thierry Reding: This contains a set of patches that extend existing bindings with support for Tegra186. * tag 'tegra-for-4.16-dt-bindings' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/tegra/linux: dt-bindings: memory: Add Tegra186 support dt-bindings: misc: Add Tegra186 MISC registers bindings
Diffstat (limited to 'Documentation/devicetree/bindings/misc')
-rw-r--r--Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt12
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diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt b/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt
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+NVIDIA Tegra186 MISC register block
+
+The MISC register block found on Tegra186 SoCs contains registers that can be
+used to identify a given chip and various strapping options.
+
+Required properties:
+- compatible: Must be:
+ - Tegra186: "nvidia,tegra186-misc"
+- reg: Should contain 2 entries: The first entry gives the physical address
+ and length of the register region which contains revision and debug
+ features. The second entry specifies the physical address and length
+ of the register region indicating the strapping options.