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author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2018-06-27 02:57:51 +0300 |
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committer | Rob Herring <robh@kernel.org> | 2018-07-10 17:08:57 +0300 |
commit | 913097bcdc9010d1617cded9f623a52438531653 (patch) | |
tree | 0db24bf7f9ee44b3b83b7c131a38547a33db3292 /Documentation/devicetree/bindings/misc | |
parent | 24a29949230c95d528d890e67004f239d4227a02 (diff) | |
download | linux-913097bcdc9010d1617cded9f623a52438531653.tar.xz |
dt-bindings: misc: ASPEED coprocessor interrupt controller
Add the device-tree binding definition for the AST2400
and AST2500 coprocessor interrupt controller
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/misc')
-rw-r--r-- | Documentation/devicetree/bindings/misc/aspeed,cvic.txt | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/misc/aspeed,cvic.txt b/Documentation/devicetree/bindings/misc/aspeed,cvic.txt new file mode 100644 index 000000000000..d62c783d1d5e --- /dev/null +++ b/Documentation/devicetree/bindings/misc/aspeed,cvic.txt @@ -0,0 +1,35 @@ +* ASPEED AST2400 and AST2500 coprocessor interrupt controller + +This file describes the bindings for the interrupt controller present +in the AST2400 and AST2500 BMC SoCs which provides interrupt to the +ColdFire coprocessor. + +It is not a normal interrupt controller and it would be rather +inconvenient to create an interrupt tree for it as it somewhat shares +some of the same sources as the main ARM interrupt controller but with +different numbers. + +The AST2500 supports a SW generated interrupt + +Required properties: +- reg: address and length of the register for the device. +- compatible: "aspeed,cvic" and one of: + "aspeed,ast2400-cvic" + or + "aspeed,ast2500-cvic" + +- valid-sources: One cell, bitmap of supported sources for the implementation + +Optional properties; +- copro-sw-interrupts: List of interrupt numbers that can be used as + SW interrupts from the ARM to the coprocessor. + (AST2500 only) + +Example: + + cvic: copro-interrupt-controller@1e6c2000 { + compatible = "aspeed,ast2500-cvic"; + valid-sources = <0xffffffff>; + copro-sw-interrupts = <1>; + reg = <0x1e6c2000 0x80>; + }; |