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authorThierry Reding <treding@nvidia.com>2020-09-17 13:07:40 +0300
committerThierry Reding <treding@nvidia.com>2020-09-18 16:54:37 +0300
commitc8f413b930058726ad0bb59ac35d9241a375e905 (patch)
treef0fa9e58ea4ad2952b10254ec4d207bf38c2e155 /Documentation/devicetree/bindings/misc
parent54cc33a3a44fc7f7d6743f7cfabc5de086a0e056 (diff)
downloadlinux-c8f413b930058726ad0bb59ac35d9241a375e905.tar.xz
dt-bindings: misc: tegra186-misc: Add missing compatible string
Add the missing compatible string for the Tegra194 MISC block. Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'Documentation/devicetree/bindings/misc')
-rw-r--r--Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt7
1 files changed, 4 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt b/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt
index 892ba4384abc..111dfac70ea7 100644
--- a/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt
+++ b/Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt
@@ -1,11 +1,12 @@
-NVIDIA Tegra186 MISC register block
+NVIDIA Tegra186 (and later) MISC register block
-The MISC register block found on Tegra186 SoCs contains registers that can be
-used to identify a given chip and various strapping options.
+The MISC register block found on Tegra186 and later SoCs contains registers
+that can be used to identify a given chip and various strapping options.
Required properties:
- compatible: Must be:
- Tegra186: "nvidia,tegra186-misc"
+ - Tegra194: "nvidia,tegra194-misc"
- reg: Should contain 2 entries: The first entry gives the physical address
and length of the register region which contains revision and debug
features. The second entry specifies the physical address and length