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| author | Jiri Kosina <jkosina@suse.cz> | 2023-11-01 02:07:35 +0300 |
|---|---|---|
| committer | Jiri Kosina <jkosina@suse.cz> | 2023-11-01 02:07:35 +0300 |
| commit | 20cd569d7ee8fce24e8753f0f43af6c420557b1f (patch) | |
| tree | f559cfda594846795aa51c99d96f92d8c912851a /Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml | |
| parent | 62cc9c3cb3ec1bf31cc116146185ed97b450836a (diff) | |
| parent | eeebfe6259ba2d5b0980eb7b0df384eb77e9e4f5 (diff) | |
| download | linux-20cd569d7ee8fce24e8753f0f43af6c420557b1f.tar.xz | |
Merge branch 'for-6.7/config_pm' into for-linus
- #ifdef CONFIG_PM removal from HID code (Thomas Weißschuh)
Diffstat (limited to 'Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml')
| -rw-r--r-- | Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml | 21 |
1 files changed, 19 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml index 89959e5c47ba..58f0cea160ef 100644 --- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml +++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml @@ -43,8 +43,10 @@ properties: - const: jedec,spi-nor - const: jedec,spi-nor description: - Must also include "jedec,spi-nor" for any SPI NOR flash that can be - identified by the JEDEC READ ID opcode (0x9F). + SPI NOR flashes compatible with the JEDEC SFDP standard or which may be + identified with the READ ID opcode (0x9F) do not deserve a specific + compatible. They should instead only be matched against the generic + "jedec,spi-nor" compatible. reg: minItems: 1 @@ -70,6 +72,21 @@ properties: be used on such systems, to denote the absence of a reliable reset mechanism. + no-wp: + type: boolean + description: + The status register write disable (SRWD) bit in status register, combined + with the WP# signal, provides hardware data protection for the device. When + the SRWD bit is set to 1, and the WP# signal is either driven LOW or hard + strapped to LOW, the status register nonvolatile bits become read-only and + the WRITE STATUS REGISTER operation will not execute. The only way to exit + this hardware-protected mode is to drive WP# HIGH. If the WP# signal of the + flash device is not connected or is wrongly tied to GND (that includes internal + pull-downs) then status register permanently becomes read-only as the SRWD bit + cannot be reset. This boolean flag can be used on such systems to avoid setting + the SRWD bit while writing the status register. WP# signal hard strapped to GND + can be a valid use case. + reset-gpios: description: A GPIO line connected to the RESET (active low) signal of the device. |