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authorHeiko Stuebner <heiko@sntech.de>2019-10-29 14:42:39 +0300
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2019-11-05 20:35:32 +0300
commitde02fc40fc63aa6950435a18e99843603b1bda01 (patch)
treee269ed80b08c5a19db86e95484e6dbbbb2511f2e /Documentation/devicetree/bindings/nvmem
parentb210fac7f636a1859cb3773a245452213fa32c59 (diff)
downloadlinux-de02fc40fc63aa6950435a18e99843603b1bda01.tar.xz
dt-bindings: nvmem: add binding for Rockchip OTP controller
Newer Rockchip SoCs use a different IP for accessing special one- time-programmable memory, so add a binding for these controllers. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Link: https://lore.kernel.org/r/20191029114240.14905-10-srinivas.kandagatla@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'Documentation/devicetree/bindings/nvmem')
-rw-r--r--Documentation/devicetree/bindings/nvmem/rockchip-otp.txt25
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diff --git a/Documentation/devicetree/bindings/nvmem/rockchip-otp.txt b/Documentation/devicetree/bindings/nvmem/rockchip-otp.txt
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+Rockchip internal OTP (One Time Programmable) memory device tree bindings
+
+Required properties:
+- compatible: Should be one of the following.
+ - "rockchip,px30-otp" - for PX30 SoCs.
+ - "rockchip,rk3308-otp" - for RK3308 SoCs.
+- reg: Should contain the registers location and size
+- clocks: Must contain an entry for each entry in clock-names.
+- clock-names: Should be "otp", "apb_pclk" and "phy".
+- resets: Must contain an entry for each entry in reset-names.
+ See ../../reset/reset.txt for details.
+- reset-names: Should be "phy".
+
+See nvmem.txt for more information.
+
+Example:
+ otp: otp@ff290000 {
+ compatible = "rockchip,px30-otp";
+ reg = <0x0 0xff290000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>,
+ <&cru PCLK_OTP_PHY>;
+ clock-names = "otp", "apb_pclk", "phy";
+ };