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| author | Richard Zhu <hongxing.zhu@nxp.com> | 2021-12-02 11:02:33 +0300 |
|---|---|---|
| committer | Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> | 2021-12-16 13:32:19 +0300 |
| commit | 3e15f623bbdf09c88763dfc3bb47fc5d7d13a62c (patch) | |
| tree | c448ccb08b09f8d944aab582b80c63d58fd76240 /Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | |
| parent | 549bf94dd29f6373154ff731d4a48e396f543363 (diff) | |
| download | linux-3e15f623bbdf09c88763dfc3bb47fc5d7d13a62c.tar.xz | |
dt-bindings: imx6q-pcie: Add PHY phandles and name properties
i.MX8MM PCIe has the PHY. Add a PHY phandle and name properties
in the binding document.
Link: https://lore.kernel.org/r/1638432158-4119-4-git-send-email-hongxing.zhu@nxp.com
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml')
| -rw-r--r-- | Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml index acea1cd444fd..643a6333b07b 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml @@ -127,6 +127,12 @@ properties: enum: [1, 2, 3, 4] default: 1 + phys: + maxItems: 1 + + phy-names: + const: pcie-phy + reset-gpio: description: Should specify the GPIO for controlling the PCI bus device reset signal. It's not polarity aware and defaults to active-low reset |