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authorGreg Kroah-Hartman <gregkh@linuxfoundation.org>2020-05-22 10:28:16 +0300
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2020-05-22 10:28:16 +0300
commit14f3a5ccacdb4268764474d834ee353219dbd1a2 (patch)
treeefbae1e87b82a81a5a72f13cfa770a8d92fa024e /Documentation/devicetree/bindings/phy
parente9ccc35b86653cb15e9bffbe2cbef8781ea2c1dd (diff)
parentac0a95a3ea7811f5cc4489924ddb54f0ea0f3007 (diff)
downloadlinux-14f3a5ccacdb4268764474d834ee353219dbd1a2.tar.xz
Merge tag 'phy-for-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy into usb-next
Kishon writes: phy: for 5.8 *) Add new PHY driver to support Cadence SALVO PHY which supports USB3 & USB2 *) Add new PHY driver to support Intel ComboPhy which supports PCIe, SATA and EMAC *) Add new PHY driver for Qualcomm IPQ40xx USB PHY *) Add new PHY driver for Synopsys FemtoPHY V2 driver used in Qualcomm SOCs *) Add support for Qualcomm SM8250 UFS PHY and SM8150 QMP USB3 PHY in qcom-qmp-phy driver *) Add support for Amlogic USB2 PHY on Meson8m2 in phy-meson8b-usb2 driver *) Add DisplayPort mode support in Wiz (TI Cadence PHY wrapper), to enable eDP in TI's J721E SoC *) Add support for super speed USB PHY in TI's AM654 SoC *) Add fix in Broadcom Stingray USB PHY to get USB PHY PLL lock reliably *) Add fix in Samsung phy-s5pv210-usb2 to get USB working on s5pv210 *) Add fix in Amlogic phy-meson8b-usb2 to get host only mode working on Meson8 *) Add fix in Cadence phy-cadence-sierra to get USB3 device disconnect issue *) Convert meson8b-usb2-phy, qcom-qmp-phy, rcar-gen3-phy-usb2 and rcar-gen3-phy-usb3 device tree binding to YAML schema *) Minor fixes and cleanups in phy-cpcap-usb, j721e-wiz, omap-usb2, phy-bcm-sr-usb, phy-brcm-usb PHY driver Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> * tag 'phy-for-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (43 commits) phy: intel: Add driver support for ComboPhy dt-bindings: phy: Add YAML schemas for Intel ComboPhy dt-bindings: phy: Add PHY_TYPE_XPCS definition phy: qcom-qmp: Add QMP V3 USB3 PHY support for SC7180 dt-bindings: phy: qcom,qmp-usb3-dp: Add support for SC7180 dt-bindings: phy: qcom,qmp-usb3-dp: Add dt bindings for USB3 DP PHY dt-bindings: phy: qcom,qmp: Convert QMP PHY bindings to yaml phy: cadence: sierra: Fix for USB3 U1/U2 state phy: ti: am654: add support for USB super-speed phy: ti: am654: show up in regmap debugfs drivers: phy: sr-usb: do not use internal fsm for USB2 phy init dt-bindings: phy: renesas: usb3-phy: add r8a77961 support dt-bindings: phy: renesas: usb3-phy: convert bindings to json-schema dt-bindings: phy: renesas: usb2-phy: add r8a77961 support dt-bindings: phy: renesas: usb2-phy: convert bindings to json-schema phy: qcom-qmp: Ensure register indirection arrays initialized phy: omap-usb2: Clean up exported header phy: phy-bcm-ns2-usbdrd: Constify phy_ops phy: phy-brcm-usb: Constify static structs phy: sr-usb: Constify phy_ops ...
Diffstat (limited to 'Documentation/devicetree/bindings/phy')
-rw-r--r--Documentation/devicetree/bindings/phy/amlogic,meson8b-usb2-phy.yaml64
-rw-r--r--Documentation/devicetree/bindings/phy/cdns,salvo-phy.yaml52
-rw-r--r--Documentation/devicetree/bindings/phy/intel,combo-phy.yaml101
-rw-r--r--Documentation/devicetree/bindings/phy/meson8b-usb2-phy.txt28
-rw-r--r--Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml313
-rw-r--r--Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml136
-rw-r--r--Documentation/devicetree/bindings/phy/qcom,usb-snps-femto-v2.yaml80
-rw-r--r--Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt242
-rw-r--r--Documentation/devicetree/bindings/phy/qcom-usb-ipq4019-phy.yaml50
-rw-r--r--Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt70
-rw-r--r--Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb3.txt52
-rw-r--r--Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml117
-rw-r--r--Documentation/devicetree/bindings/phy/renesas,usb3-phy.yaml79
13 files changed, 992 insertions, 392 deletions
diff --git a/Documentation/devicetree/bindings/phy/amlogic,meson8b-usb2-phy.yaml b/Documentation/devicetree/bindings/phy/amlogic,meson8b-usb2-phy.yaml
new file mode 100644
index 000000000000..03c4809dbe8d
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/amlogic,meson8b-usb2-phy.yaml
@@ -0,0 +1,64 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/phy/amlogic,meson8b-usb2-phy.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Amlogic Meson8, Meson8b, Meson8m2 and GXBB USB2 PHY
+
+maintainers:
+ - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - amlogic,meson8-usb2-phy
+ - amlogic,meson8b-usb2-phy
+ - amlogic,meson8m2-usb2-phy
+ - const: amlogic,meson-mx-usb2-phy
+ - const: amlogic,meson-gxbb-usb2-phy
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 2
+
+ clock-names:
+ items:
+ - const: usb_general
+ - const: usb
+
+ resets:
+ minItems: 1
+
+ "#phy-cells":
+ const: 0
+
+ phy-supply:
+ description:
+ Phandle to a regulator that provides power to the PHY. This
+ regulator will be managed during the PHY power on/off sequence.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ usb-phy@c0000000 {
+ compatible = "amlogic,meson-gxbb-usb2-phy";
+ reg = <0xc0000000 0x20>;
+ resets = <&reset_usb_phy>;
+ clocks = <&clk_usb_general>, <&reset_usb>;
+ clock-names = "usb_general", "usb";
+ phy-supply = <&usb_vbus>;
+ #phy-cells = <0>;
+ };
diff --git a/Documentation/devicetree/bindings/phy/cdns,salvo-phy.yaml b/Documentation/devicetree/bindings/phy/cdns,salvo-phy.yaml
new file mode 100644
index 000000000000..3a07285b5470
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/cdns,salvo-phy.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright (c) 2020 NXP
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/phy/cdns,salvo-phy.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Cadence SALVO PHY
+
+maintainers:
+ - Peter Chen <peter.chen@nxp.com>
+
+properties:
+ compatible:
+ enum:
+ - nxp,salvo-phy
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: salvo_phy_clk
+
+ power-domains:
+ maxItems: 1
+
+ "#phy-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/firmware/imx/rsrc.h>
+
+ usb3phy: usb3-phy@5b160000 {
+ compatible = "nxp,salvo-phy";
+ reg = <0x5b160000 0x40000>;
+ clocks = <&usb3_lpcg 4>;
+ clock-names = "salvo_phy_clk";
+ power-domains = <&pd IMX_SC_R_USB_2_PHY>;
+ #phy-cells = <0>;
+ };
diff --git a/Documentation/devicetree/bindings/phy/intel,combo-phy.yaml b/Documentation/devicetree/bindings/phy/intel,combo-phy.yaml
new file mode 100644
index 000000000000..347d0cdfb80d
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/intel,combo-phy.yaml
@@ -0,0 +1,101 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/intel,combo-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Intel ComboPhy Subsystem
+
+maintainers:
+ - Dilip Kota <eswara.kota@linux.intel.com>
+
+description: |
+ Intel Combophy subsystem supports PHYs for PCIe, EMAC and SATA
+ controllers. A single Combophy provides two PHY instances.
+
+properties:
+ $nodename:
+ pattern: "combophy(@.*|-[0-9a-f])*$"
+
+ compatible:
+ items:
+ - const: intel,combophy-lgm
+ - const: intel,combo-phy
+
+ clocks:
+ maxItems: 1
+
+ reg:
+ items:
+ - description: ComboPhy core registers
+ - description: PCIe app core control registers
+
+ reg-names:
+ items:
+ - const: core
+ - const: app
+
+ resets:
+ maxItems: 4
+
+ reset-names:
+ items:
+ - const: phy
+ - const: core
+ - const: iphy0
+ - const: iphy1
+
+ intel,syscfg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: Chip configuration registers handle and ComboPhy instance id
+
+ intel,hsio:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: HSIO registers handle and ComboPhy instance id on NOC
+
+ intel,aggregation:
+ type: boolean
+ description: |
+ Specify the flag to configure ComboPHY in dual lane mode.
+
+ intel,phy-mode:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Mode of the two phys in ComboPhy.
+ See dt-bindings/phy/phy.h for values.
+
+ "#phy-cells":
+ const: 1
+
+required:
+ - compatible
+ - clocks
+ - reg
+ - reg-names
+ - intel,syscfg
+ - intel,hsio
+ - intel,phy-mode
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/phy/phy.h>
+ combophy@d0a00000 {
+ compatible = "intel,combophy-lgm", "intel,combo-phy";
+ clocks = <&cgu0 1>;
+ #phy-cells = <1>;
+ reg = <0xd0a00000 0x40000>,
+ <0xd0a40000 0x1000>;
+ reg-names = "core", "app";
+ resets = <&rcu0 0x50 6>,
+ <&rcu0 0x50 17>,
+ <&rcu0 0x50 23>,
+ <&rcu0 0x50 24>;
+ reset-names = "phy", "core", "iphy0", "iphy1";
+ intel,syscfg = <&sysconf 0>;
+ intel,hsio = <&hsiol 0>;
+ intel,phy-mode = <PHY_TYPE_PCIE>;
+ intel,aggregation;
+ };
diff --git a/Documentation/devicetree/bindings/phy/meson8b-usb2-phy.txt b/Documentation/devicetree/bindings/phy/meson8b-usb2-phy.txt
deleted file mode 100644
index d81d73aea608..000000000000
--- a/Documentation/devicetree/bindings/phy/meson8b-usb2-phy.txt
+++ /dev/null
@@ -1,28 +0,0 @@
-* Amlogic Meson8, Meson8b and GXBB USB2 PHY
-
-Required properties:
-- compatible: Depending on the platform this should be one of:
- "amlogic,meson8-usb2-phy"
- "amlogic,meson8b-usb2-phy"
- "amlogic,meson-gxbb-usb2-phy"
-- reg: The base address and length of the registers
-- #phys-cells: should be 0 (see phy-bindings.txt in this directory)
-- clocks: phandle and clock identifier for the phy clocks
-- clock-names: "usb_general" and "usb"
-
-Optional properties:
-- resets: reference to the reset controller
-- phy-supply: see phy-bindings.txt in this directory
-
-
-Example:
-
-usb0_phy: usb-phy@c0000000 {
- compatible = "amlogic,meson-gxbb-usb2-phy";
- #phy-cells = <0>;
- reg = <0x0 0xc0000000 0x0 0x20>;
- resets = <&reset RESET_USB_OTG>;
- clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
- clock-names = "usb_general", "usb";
- phy-supply = <&usb_vbus>;
-};
diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
new file mode 100644
index 000000000000..973b2d196f46
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
@@ -0,0 +1,313 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/phy/qcom,qmp-phy.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Qualcomm QMP PHY controller
+
+maintainers:
+ - Manu Gautam <mgautam@codeaurora.org>
+
+description:
+ QMP phy controller supports physical layer functionality for a number of
+ controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
+
+properties:
+ compatible:
+ enum:
+ - qcom,ipq8074-qmp-pcie-phy
+ - qcom,msm8996-qmp-pcie-phy
+ - qcom,msm8996-qmp-ufs-phy
+ - qcom,msm8996-qmp-usb3-phy
+ - qcom,msm8998-qmp-pcie-phy
+ - qcom,msm8998-qmp-ufs-phy
+ - qcom,msm8998-qmp-usb3-phy
+ - qcom,sdm845-qhp-pcie-phy
+ - qcom,sdm845-qmp-pcie-phy
+ - qcom,sdm845-qmp-ufs-phy
+ - qcom,sdm845-qmp-usb3-uni-phy
+ - qcom,sm8150-qmp-ufs-phy
+ - qcom,sm8250-qmp-ufs-phy
+
+ reg:
+ items:
+ - description: Address and length of PHY's common serdes block.
+
+ "#clock-cells":
+ enum: [ 1, 2 ]
+
+ "#address-cells":
+ enum: [ 1, 2 ]
+
+ "#size-cells":
+ enum: [ 1, 2 ]
+
+ clocks:
+ minItems: 1
+ maxItems: 4
+
+ clock-names:
+ minItems: 1
+ maxItems: 4
+
+ resets:
+ minItems: 1
+ maxItems: 3
+
+ reset-names:
+ minItems: 1
+ maxItems: 3
+
+ vdda-phy-supply:
+ description:
+ Phandle to a regulator supply to PHY core block.
+
+ vdda-pll-supply:
+ description:
+ Phandle to 1.8V regulator supply to PHY refclk pll block.
+
+ vddp-ref-clk-supply:
+ description:
+ Phandle to a regulator supply to any specific refclk
+ pll block.
+
+#Required nodes:
+patternProperties:
+ "^phy@[0-9a-f]+$":
+ type: object
+ description:
+ Each device node of QMP phy is required to have as many child nodes as
+ the number of lanes the PHY has.
+
+required:
+ - compatible
+ - reg
+ - "#clock-cells"
+ - "#address-cells"
+ - "#size-cells"
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ - vdda-phy-supply
+ - vdda-pll-supply
+
+additionalProperties: false
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sdm845-qmp-usb3-uni-phy
+ then:
+ properties:
+ clocks:
+ items:
+ - description: Phy aux clock.
+ - description: Phy config clock.
+ - description: 19.2 MHz ref clk.
+ - description: Phy common block aux clock.
+ clock-names:
+ items:
+ - const: aux
+ - const: cfg_ahb
+ - const: ref
+ - const: com_aux
+ resets:
+ items:
+ - description: reset of phy block.
+ - description: phy common block reset.
+ reset-names:
+ items:
+ - const: phy
+ - const: common
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,msm8996-qmp-pcie-phy
+ then:
+ properties:
+ clocks:
+ items:
+ - description: Phy aux clock.
+ - description: Phy config clock.
+ - description: 19.2 MHz ref clk.
+ clock-names:
+ items:
+ - const: aux
+ - const: cfg_ahb
+ - const: ref
+ resets:
+ items:
+ - description: reset of phy block.
+ - description: phy common block reset.
+ - description: phy's ahb cfg block reset.
+ reset-names:
+ items:
+ - const: phy
+ - const: common
+ - const: cfg
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,msm8996-qmp-usb3-phy
+ - qcom,msm8998-qmp-pcie-phy
+ - qcom,msm8998-qmp-usb3-phy
+ then:
+ properties:
+ clocks:
+ items:
+ - description: Phy aux clock.
+ - description: Phy config clock.
+ - description: 19.2 MHz ref clk.
+ clock-names:
+ items:
+ - const: aux
+ - const: cfg_ahb
+ - const: ref
+ resets:
+ items:
+ - description: reset of phy block.
+ - description: phy common block reset.
+ reset-names:
+ items:
+ - const: phy
+ - const: common
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,msm8996-qmp-ufs-phy
+ then:
+ properties:
+ clocks:
+ items:
+ - description: 19.2 MHz ref clk.
+ clock-names:
+ items:
+ - const: ref
+ resets:
+ items:
+ - description: PHY reset in the UFS controller.
+ reset-names:
+ items:
+ - const: ufsphy
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,msm8998-qmp-ufs-phy
+ - qcom,sdm845-qmp-ufs-phy
+ - qcom,sm8150-qmp-ufs-phy
+ - qcom,sm8250-qmp-ufs-phy
+ then:
+ properties:
+ clocks:
+ items:
+ - description: 19.2 MHz ref clk.
+ - description: Phy reference aux clock.
+ clock-names:
+ items:
+ - const: ref
+ - const: ref_aux
+ resets:
+ items:
+ - description: PHY reset in the UFS controller.
+ reset-names:
+ items:
+ - const: ufsphy
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,ipq8074-qmp-pcie-phy
+ then:
+ properties:
+ clocks:
+ items:
+ - description: pipe clk.
+ clock-names:
+ items:
+ - const: pipe_clk
+ resets:
+ items:
+ - description: reset of phy block.
+ - description: phy common block reset.
+ reset-names:
+ items:
+ - const: phy
+ - const: common
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sdm845-qhp-pcie-phy
+ - qcom,sdm845-qmp-pcie-phy
+ then:
+ properties:
+ clocks:
+ items:
+ - description: Phy aux clock.
+ - description: Phy config clock.
+ - description: 19.2 MHz ref clk.
+ - description: Phy refgen clk.
+ clock-names:
+ items:
+ - const: aux
+ - const: cfg_ahb
+ - const: ref
+ - const: refgen
+ resets:
+ items:
+ - description: reset of phy block.
+ reset-names:
+ items:
+ - const: phy
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-sdm845.h>
+ usb_2_qmpphy: phy-wrapper@88eb000 {
+ compatible = "qcom,sdm845-qmp-usb3-uni-phy";
+ reg = <0 0x088eb000 0 0x18c>;
+ #clock-cells = <1>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK >,
+ <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+ <&gcc GCC_USB3_SEC_CLKREF_CLK>,
+ <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
+ clock-names = "aux", "cfg_ahb", "ref", "com_aux";
+
+ resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
+ <&gcc GCC_USB3_PHY_SEC_BCR>;
+ reset-names = "phy", "common";
+
+ vdda-phy-supply = <&vdda_usb2_ss_1p2>;
+ vdda-pll-supply = <&vdda_usb2_ss_core>;
+
+ usb_2_ssphy: phy@88eb200 {
+ reg = <0 0x088eb200 0 0x128>,
+ <0 0x088eb400 0 0x1fc>,
+ <0 0x088eb800 0 0x218>,
+ <0 0x088eb600 0 0x70>;
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+ clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
+ clock-names = "pipe0";
+ clock-output-names = "usb3_uni_phy_pipe_clk_src";
+ };
+ };
diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml
new file mode 100644
index 000000000000..b770e637df1d
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml
@@ -0,0 +1,136 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/phy/qcom,qmp-usb3-dp-phy.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Qualcomm QMP USB3 DP PHY controller
+
+maintainers:
+ - Manu Gautam <mgautam@codeaurora.org>
+
+properties:
+ compatible:
+ enum:
+ - qcom,sc7180-qmp-usb3-phy
+ - qcom,sdm845-qmp-usb3-phy
+ reg:
+ items:
+ - description: Address and length of PHY's common serdes block.
+ - description: Address and length of the DP_COM control block.
+
+ reg-names:
+ items:
+ - const: reg-base
+ - const: dp_com
+
+ "#clock-cells":
+ enum: [ 1, 2 ]
+
+ "#address-cells":
+ enum: [ 1, 2 ]
+
+ "#size-cells":
+ enum: [ 1, 2 ]
+
+ clocks:
+ items:
+ - description: Phy aux clock.
+ - description: Phy config clock.
+ - description: 19.2 MHz ref clk.
+ - description: Phy common block aux clock.
+
+ clock-names:
+ items:
+ - const: aux
+ - const: cfg_ahb
+ - const: ref
+ - const: com_aux
+
+ resets:
+ items:
+ - description: reset of phy block.
+ - description: phy common block reset.
+
+ reset-names:
+ items:
+ - const: phy
+ - const: common
+
+ vdda-phy-supply:
+ description:
+ Phandle to a regulator supply to PHY core block.
+
+ vdda-pll-supply:
+ description:
+ Phandle to 1.8V regulator supply to PHY refclk pll block.
+
+ vddp-ref-clk-supply:
+ description:
+ Phandle to a regulator supply to any specific refclk
+ pll block.
+
+#Required nodes:
+patternProperties:
+ "^phy@[0-9a-f]+$":
+ type: object
+ description:
+ Each device node of QMP phy is required to have as many child nodes as
+ the number of lanes the PHY has.
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - "#clock-cells"
+ - "#address-cells"
+ - "#size-cells"
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ - vdda-phy-supply
+ - vdda-pll-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-sdm845.h>
+ usb_1_qmpphy: phy-wrapper@88e9000 {
+ compatible = "qcom,sdm845-qmp-usb3-phy";
+ reg = <0 0x088e9000 0 0x18c>,
+ <0 0x088e8000 0 0x10>;
+ reg-names = "reg-base", "dp_com";
+ #clock-cells = <1>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
+ <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+ <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
+ <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
+ clock-names = "aux", "cfg_ahb", "ref", "com_aux";
+
+ resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
+ <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
+ reset-names = "phy", "common";
+
+ vdda-phy-supply = <&vdda_usb2_ss_1p2>;
+ vdda-pll-supply = <&vdda_usb2_ss_core>;
+
+ usb_1_ssphy: phy@88e9200 {
+ reg = <0 0x088e9200 0 0x128>,
+ <0 0x088e9400 0 0x200>,
+ <0 0x088e9c00 0 0x218>,
+ <0 0x088e9600 0 0x128>,
+ <0 0x088e9800 0 0x200>,
+ <0 0x088e9a00 0 0x100>;
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+ clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+ clock-names = "pipe0";
+ clock-output-names = "usb3_phy_pipe_clk_src";
+ };
+ };
diff --git a/Documentation/devicetree/bindings/phy/qcom,usb-snps-femto-v2.yaml b/Documentation/devicetree/bindings/phy/qcom,usb-snps-femto-v2.yaml
new file mode 100644
index 000000000000..574f890fab1d
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom,usb-snps-femto-v2.yaml
@@ -0,0 +1,80 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/phy/qcom,usb-snps-femto-v2.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Qualcomm Synopsys Femto High-Speed USB PHY V2
+
+maintainers:
+ - Wesley Cheng <wcheng@codeaurora.org>
+
+description: |
+ Qualcomm High-Speed USB PHY
+
+properties:
+ compatible:
+ enum:
+ - qcom,usb-snps-hs-7nm-phy
+ - qcom,sm8150-usb-hs-phy
+ - qcom,usb-snps-femto-v2-phy
+
+ reg:
+ maxItems: 1
+
+ "#phy-cells":
+ const: 0
+
+ clocks:
+ items:
+ - description: rpmhcc ref clock
+
+ clock-names:
+ items:
+ - const: ref
+
+ resets:
+ items:
+ - description: PHY core reset
+
+ vdda-pll-supply:
+ description: phandle to the regulator VDD supply node.
+
+ vdda18-supply:
+ description: phandle to the regulator 1.8V supply node.
+
+ vdda33-supply:
+ description: phandle to the regulator 3.3V supply node.
+
+required:
+ - compatible
+ - reg
+ - "#phy-cells"
+ - clocks
+ - clock-names
+ - resets
+ - vdda-pll-supply
+ - vdda18-supply
+ - vdda33-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/clock/qcom,gcc-sm8150.h>
+ phy@88e2000 {
+ compatible = "qcom,sm8150-usb-hs-phy";
+ reg = <0 0x088e2000 0 0x400>;
+ #phy-cells = <0>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "ref";
+
+ resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+
+ vdda-pll-supply = <&vdd_usb_hs_core>;
+ vdda33-supply = <&vdda_usb_hs_3p1>;
+ vdda18-supply = <&vdda_usb_hs_1p8>;
+ };
+...
diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
deleted file mode 100644
index 54d6f8d43508..000000000000
--- a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
+++ /dev/null
@@ -1,242 +0,0 @@
-Qualcomm QMP PHY controller
-===========================
-
-QMP phy controller supports physical layer functionality for a number of
-controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
-
-Required properties:
- - compatible: compatible list, contains:
- "qcom,ipq8074-qmp-pcie-phy" for PCIe phy on IPQ8074
- "qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,
- "qcom,msm8996-qmp-ufs-phy" for 14nm UFS phy on msm8996,
- "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996,
- "qcom,msm8998-qmp-usb3-phy" for USB3 QMP V3 phy on msm8998,
- "qcom,msm8998-qmp-ufs-phy" for UFS QMP phy on msm8998,
- "qcom,msm8998-qmp-pcie-phy" for PCIe QMP phy on msm8998,
- "qcom,sdm845-qhp-pcie-phy" for QHP PCIe phy on sdm845,
- "qcom,sdm845-qmp-pcie-phy" for QMP PCIe phy on sdm845,
- "qcom,sdm845-qmp-usb3-phy" for USB3 QMP V3 phy on sdm845,
- "qcom,sdm845-qmp-usb3-uni-phy" for USB3 QMP V3 UNI phy on sdm845,
- "qcom,sdm845-qmp-ufs-phy" for UFS QMP phy on sdm845,
- "qcom,sm8150-qmp-ufs-phy" for UFS QMP phy on sm8150.
-
-- reg:
- - index 0: address and length of register set for PHY's common
- serdes block.
- - index 1: address and length of the DP_COM control block (for
- "qcom,sdm845-qmp-usb3-phy" only).
-
-- reg-names:
- - For "qcom,sdm845-qmp-usb3-phy":
- - Should be: "reg-base", "dp_com"
- - For all others:
- - The reg-names property shouldn't be defined.
-
- - #address-cells: must be 1
- - #size-cells: must be 1
- - ranges: must be present
-
- - clocks: a list of phandles and clock-specifier pairs,
- one for each entry in clock-names.
- - clock-names: "cfg_ahb" for phy config clock,
- "aux" for phy aux clock,
- "ref" for 19.2 MHz ref clk,
- "com_aux" for phy common block aux clock,
- "ref_aux" for phy reference aux clock,
-
- For "qcom,ipq8074-qmp-pcie-phy": no clocks are listed.
- For "qcom,msm8996-qmp-pcie-phy" must contain:
- "aux", "cfg_ahb", "ref".
- For "qcom,msm8996-qmp-ufs-phy" must contain:
- "ref".
- For "qcom,msm8996-qmp-usb3-phy" must contain:
- "aux", "cfg_ahb", "ref".
- For "qcom,msm8998-qmp-usb3-phy" must contain:
- "aux", "cfg_ahb", "ref".
- For "qcom,msm8998-qmp-ufs-phy" must contain:
- "ref", "ref_aux".
- For "qcom,msm8998-qmp-pcie-phy" must contain:
- "aux", "cfg_ahb", "ref".
- For "qcom,sdm845-qhp-pcie-phy" must contain:
- "aux", "cfg_ahb", "ref", "refgen".
- For "qcom,sdm845-qmp-pcie-phy" must contain:
- "aux", "cfg_ahb", "ref", "refgen".
- For "qcom,sdm845-qmp-usb3-phy" must contain:
- "aux", "cfg_ahb", "ref", "com_aux".
- For "qcom,sdm845-qmp-usb3-uni-phy" must contain:
- "aux", "cfg_ahb", "ref", "com_aux".
- For "qcom,sdm845-qmp-ufs-phy" must contain:
- "ref", "ref_aux".
- For "qcom,sm8150-qmp-ufs-phy" must contain:
- "ref", "ref_aux".
-
- - resets: a list of phandles and reset controller specifier pairs,
- one for each entry in reset-names.
- - reset-names: "phy" for reset of phy block,
- "common" for phy common block reset,
- "cfg" for phy's ahb cfg block reset,
- "ufsphy" for the PHY reset in the UFS controller.
-
- For "qcom,ipq8074-qmp-pcie-phy" must contain:
- "phy", "common".
- For "qcom,msm8996-qmp-pcie-phy" must contain:
- "phy", "common", "cfg".
- For "qcom,msm8996-qmp-ufs-phy": must contain:
- "ufsphy".
- For "qcom,msm8996-qmp-usb3-phy" must contain
- "phy", "common".
- For "qcom,msm8998-qmp-usb3-phy" must contain
- "phy", "common".
- For "qcom,msm8998-qmp-ufs-phy": must contain:
- "ufsphy".
- For "qcom,msm8998-qmp-pcie-phy" must contain:
- "phy", "common".
- For "qcom,sdm845-qhp-pcie-phy" must contain:
- "phy".
- For "qcom,sdm845-qmp-pcie-phy" must contain:
- "phy".
- For "qcom,sdm845-qmp-usb3-phy" must contain:
- "phy", "common".
- For "qcom,sdm845-qmp-usb3-uni-phy" must contain:
- "phy", "common".
- For "qcom,sdm845-qmp-ufs-phy": must contain:
- "ufsphy".
- For "qcom,sm8150-qmp-ufs-phy": must contain:
- "ufsphy".
-
- - vdda-phy-supply: Phandle to a regulator supply to PHY core block.
- - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.
-
-Optional properties:
- - vddp-ref-clk-supply: Phandle to a regulator supply to any specific refclk
- pll block.
-
-Required nodes:
- - Each device node of QMP phy is required to have as many child nodes as
- the number of lanes the PHY has.
-
-Required properties for child nodes of PCIe PHYs (one child per lane):
- - reg: list of offset and length pairs of register sets for PHY blocks -
- tx, rx, pcs, and pcs_misc (optional).
- - #phy-cells: must be 0
-
-Required properties for a single "lanes" child node of non-PCIe PHYs:
- - reg: list of offset and length pairs of register sets for PHY blocks
- For 1-lane devices:
- tx, rx, pcs, and (optionally) pcs_misc
- For 2-lane devices:
- tx0, rx0, pcs, tx1, rx1, and (optionally) pcs_misc
- - #phy-cells: must be 0
-
-Required properties for child node of PCIe and USB3 qmp phys:
- - clocks: a list of phandles and clock-specifier pairs,
- one for each entry in clock-names.
- - clock-names: Must contain following:
- "pipe<lane-number>" for pipe clock specific to each lane.
- - clock-output-names: Name of the PHY clock that will be the parent for
- the above pipe clock.
- For "qcom,ipq8074-qmp-pcie-phy":
- - "pcie20_phy0_pipe_clk" Pipe Clock parent
- (or)
- "pcie20_phy1_pipe_clk"
- - #clock-cells: must be 0
- - Phy pll outputs pipe clocks for pipe based PHYs. These clocks are then
- gate-controlled by the gcc.
-
-Required properties for child node of PHYs with lane reset, AKA:
- "qcom,msm8996-qmp-pcie-phy"
- - resets: a list of phandles and reset controller specifier pairs,
- one for each entry in reset-names.
- - reset-names: Must contain following:
- "lane<lane-number>" for reset specific to each lane.
-
-Example:
- phy@34000 {
- compatible = "qcom,msm8996-qmp-pcie-phy";
- reg = <0x34000 0x488>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
- <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
- <&gcc GCC_PCIE_CLKREF_CLK>;
- clock-names = "aux", "cfg_ahb", "ref";
-
- vdda-phy-supply = <&pm8994_l28>;
- vdda-pll-supply = <&pm8994_l12>;
-
- resets = <&gcc GCC_PCIE_PHY_BCR>,
- <&gcc GCC_PCIE_PHY_COM_BCR>,
- <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
- reset-names = "phy", "common", "cfg";
-
- pciephy_0: lane@35000 {
- reg = <0x35000 0x130>,
- <0x35200 0x200>,
- <0x35400 0x1dc>;
- #clock-cells = <0>;
- #phy-cells = <0>;
-
- clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "pcie_0_pipe_clk_src";
- resets = <&gcc GCC_PCIE_0_PHY_BCR>;
- reset-names = "lane0";
- };
-
- pciephy_1: lane@36000 {
- ...
- ...
- };
-
- phy@88eb000 {
- compatible = "qcom,sdm845-qmp-usb3-uni-phy";
- reg = <0x88eb000 0x18c>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
- <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
- <&gcc GCC_USB3_SEC_CLKREF_CLK>,
- <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
- clock-names = "aux", "cfg_ahb", "ref", "com_aux";
-
- resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
- <&gcc GCC_USB3_PHY_SEC_BCR>;
- reset-names = "phy", "common";
-
- lane@88eb200 {
- reg = <0x88eb200 0x128>,
- <0x88eb400 0x1fc>,
- <0x88eb800 0x218>,
- <0x88eb600 0x70>;
- #clock-cells = <0>;
- #phy-cells = <0>;
- clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "usb3_uni_phy_pipe_clk_src";
- };
- };
-
- phy@1d87000 {
- compatible = "qcom,sdm845-qmp-ufs-phy";
- reg = <0x1d87000 0x18c>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- clock-names = "ref",
- "ref_aux";
- clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
- <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
-
- lanes@1d87400 {
- reg = <0x1d87400 0x108>,
- <0x1d87600 0x1e0>,
- <0x1d87c00 0x1dc>,
- <0x1d87800 0x108>,
- <0x1d87a00 0x1e0>;
- #phy-cells = <0>;
- };
- };
diff --git a/Documentation/devicetree/bindings/phy/qcom-usb-ipq4019-phy.yaml b/Documentation/devicetree/bindings/phy/qcom-usb-ipq4019-phy.yaml
new file mode 100644
index 000000000000..1118fe69b611
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom-usb-ipq4019-phy.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/phy/qcom-usb-ipq4019-phy.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Qualcom IPQ40xx Dakota HS/SS USB PHY
+
+maintainers:
+ - Robert Marko <robert.marko@sartura.hr>
+
+properties:
+ compatible:
+ enum:
+ - qcom,usb-ss-ipq4019-phy
+ - qcom,usb-hs-ipq4019-phy
+
+ reg:
+ maxItems: 1
+
+ resets:
+ maxItems: 2
+
+ reset-names:
+ items:
+ - const: por_rst
+ - const: srif_rst
+
+ "#phy-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - resets
+ - reset-names
+ - "#phy-cells"
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
+
+ hsphy@a8000 {
+ #phy-cells = <0>;
+ compatible = "qcom,usb-hs-ipq4019-phy";
+ reg = <0xa8000 0x40>;
+ resets = <&gcc USB2_HSPHY_POR_ARES>,
+ <&gcc USB2_HSPHY_S_ARES>;
+ reset-names = "por_rst", "srif_rst";
+ };
diff --git a/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt b/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt
deleted file mode 100644
index 7734b219d9aa..000000000000
--- a/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt
+++ /dev/null
@@ -1,70 +0,0 @@
-* Renesas R-Car generation 3 USB 2.0 PHY
-
-This file provides information on what the device node for the R-Car generation
-3, RZ/G1C, RZ/G2 and RZ/A2 USB 2.0 PHY contain.
-
-Required properties:
-- compatible: "renesas,usb2-phy-r7s9210" if the device is a part of an R7S9210
- SoC.
- "renesas,usb2-phy-r8a77470" if the device is a part of an R8A77470
- SoC.
- "renesas,usb2-phy-r8a774a1" if the device is a part of an R8A774A1
- SoC.
- "renesas,usb2-phy-r8a774b1" if the device is a part of an R8A774B1
- SoC.
- "renesas,usb2-phy-r8a774c0" if the device is a part of an R8A774C0
- SoC.
- "renesas,usb2-phy-r8a7795" if the device is a part of an R8A7795
- SoC.
- "renesas,usb2-phy-r8a7796" if the device is a part of an R8A7796
- SoC.
- "renesas,usb2-phy-r8a77965" if the device is a part of an
- R8A77965 SoC.
- "renesas,usb2-phy-r8a77990" if the device is a part of an
- R8A77990 SoC.
- "renesas,usb2-phy-r8a77995" if the device is a part of an
- R8A77995 SoC.
- "renesas,rcar-gen3-usb2-phy" for a generic R-Car Gen3, RZ/G2 or
- RZ/A2 compatible device.
-
- When compatible with the generic version, nodes must list the
- SoC-specific version corresponding to the platform first
- followed by the generic version.
-
-- reg: offset and length of the partial USB 2.0 Host register block.
-- clocks: clock phandle and specifier pair(s).
-- #phy-cells: see phy-bindings.txt in the same directory, must be <1> (and
- using <0> is deprecated).
-
-The phandle's argument in the PHY specifier is the INT_STATUS bit of controller:
-- 1 = USBH_INTA (OHCI)
-- 2 = USBH_INTB (EHCI)
-- 3 = UCOM_INT (OTG and BC)
-
-Optional properties:
-To use a USB channel where USB 2.0 Host and HSUSB (USB 2.0 Peripheral) are
-combined, the device tree node should set interrupt properties to use the
-channel as USB OTG:
-- interrupts: interrupt specifier for the PHY.
-- vbus-supply: Phandle to a regulator that provides power to the VBUS. This
- regulator will be managed during the PHY power on/off sequence.
-- renesas,no-otg-pins: boolean, specify when a board does not provide proper
- otg pins.
-- dr_mode: string, indicates the working mode for the PHY. Can be "host",
- "peripheral", or "otg". Should be set if otg controller is not used.
-
-
-Example (R-Car H3):
-
- usb-phy@ee080200 {
- compatible = "renesas,usb2-phy-r8a7795", "renesas,rcar-gen3-usb2-phy";
- reg = <0 0xee080200 0 0x700>;
- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 703>;
- };
-
- usb-phy@ee0a0200 {
- compatible = "renesas,usb2-phy-r8a7795", "renesas,rcar-gen3-usb2-phy";
- reg = <0 0xee0a0200 0 0x700>;
- clocks = <&cpg CPG_MOD 702>;
- };
diff --git a/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb3.txt b/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb3.txt
deleted file mode 100644
index 0fe433b9a592..000000000000
--- a/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb3.txt
+++ /dev/null
@@ -1,52 +0,0 @@
-* Renesas R-Car generation 3 USB 3.0 PHY
-
-This file provides information on what the device node for the R-Car generation
-3 and RZ/G2 USB 3.0 PHY contain.
-If you want to enable spread spectrum clock (ssc), you should use USB_EXTAL
-instead of USB3_CLK. However, if you don't want to these features, you don't
-need this driver.
-
-Required properties:
-- compatible: "renesas,r8a774a1-usb3-phy" if the device is a part of an R8A774A1
- SoC.
- "renesas,r8a774b1-usb3-phy" if the device is a part of an R8A774B1
- SoC.
- "renesas,r8a7795-usb3-phy" if the device is a part of an R8A7795
- SoC.
- "renesas,r8a7796-usb3-phy" if the device is a part of an R8A7796
- SoC.
- "renesas,r8a77965-usb3-phy" if the device is a part of an
- R8A77965 SoC.
- "renesas,rcar-gen3-usb3-phy" for a generic R-Car Gen3 or RZ/G2
- compatible device.
-
- When compatible with the generic version, nodes must list the
- SoC-specific version corresponding to the platform first
- followed by the generic version.
-
-- reg: offset and length of the USB 3.0 PHY register block.
-- clocks: A list of phandles and clock-specifier pairs.
-- clock-names: Name of the clocks.
- - The funcional clock must be "usb3-if".
- - The usb3's external clock must be "usb3s_clk".
- - The usb2's external clock must be "usb_extal". If you want to use the ssc,
- the clock-frequency must not be 0.
-- #phy-cells: see phy-bindings.txt in the same directory, must be <0>.
-
-Optional properties:
-- renesas,ssc-range: Enable/disable spread spectrum clock (ssc) by using
- the following values as u32:
- - 0 (or the property doesn't exist): disable the ssc
- - 4980: enable the ssc as -4980 ppm
- - 4492: enable the ssc as -4492 ppm
- - 4003: enable the ssc as -4003 ppm
-
-Example (R-Car H3):
-
- usb-phy@e65ee000 {
- compatible = "renesas,r8a7795-usb3-phy",
- "renesas,rcar-gen3-usb3-phy";
- reg = <0 0xe65ee000 0 0x90>;
- clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, <&usb_extal>;
- clock-names = "usb3-if", "usb3s_clk", "usb_extal";
- };
diff --git a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
new file mode 100644
index 000000000000..440f09fddf93
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
@@ -0,0 +1,117 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/renesas,usb2-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas R-Car generation 3 USB 2.0 PHY
+
+maintainers:
+ - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: renesas,usb2-phy-r8a77470 # RZ/G1C
+
+ - items:
+ - enum:
+ - renesas,usb2-phy-r7s9210 # RZ/A2
+ - renesas,usb2-phy-r8a774a1 # RZ/G2M
+ - renesas,usb2-phy-r8a774b1 # RZ/G2N
+ - renesas,usb2-phy-r8a774c0 # RZ/G2E
+ - renesas,usb2-phy-r8a7795 # R-Car H3
+ - renesas,usb2-phy-r8a7796 # R-Car M3-W
+ - renesas,usb2-phy-r8a77961 # R-Car M3-W+
+ - renesas,usb2-phy-r8a77965 # R-Car M3-N
+ - renesas,usb2-phy-r8a77990 # R-Car E3
+ - renesas,usb2-phy-r8a77995 # R-Car D3
+ - const: renesas,rcar-gen3-usb2-phy
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ maxItems: 2
+
+ clock-names:
+ minItems: 1
+ maxItems: 2
+ items:
+ - const: fck
+ - const: usb_x1
+
+ '#phy-cells':
+ enum: [0, 1] # and 0 is deprecated.
+ description: |
+ The phandle's argument in the PHY specifier is the INT_STATUS bit of
+ controller.
+ - 1 = USBH_INTA (OHCI)
+ - 2 = USBH_INTB (EHCI)
+ - 3 = UCOM_INT (OTG and BC)
+
+ interrupts:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ minItems: 1
+ maxItems: 2
+ items:
+ - description: reset of USB 2.0 host side
+ - description: reset of USB 2.0 peripheral side
+
+ vbus-supply:
+ description: |
+ Phandle to a regulator that provides power to the VBUS. This regulator
+ will be managed during the PHY power on/off sequence.
+
+ renesas,no-otg-pins:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: |
+ specify when a board does not provide proper otg pins.
+
+ dr_mode: true
+
+if:
+ properties:
+ compatible:
+ items:
+ enum:
+ - renesas,usb2-phy-r7s9210
+then:
+ required:
+ - clock-names
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - '#phy-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/r8a7795-sysc.h>
+
+ usb-phy@ee080200 {
+ compatible = "renesas,usb2-phy-r8a7795", "renesas,rcar-gen3-usb2-phy";
+ reg = <0xee080200 0x700>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 703>;
+ #phy-cells = <1>;
+ };
+
+ usb-phy@ee0a0200 {
+ compatible = "renesas,usb2-phy-r8a7795", "renesas,rcar-gen3-usb2-phy";
+ reg = <0xee0a0200 0x700>;
+ clocks = <&cpg CPG_MOD 702>;
+ #phy-cells = <1>;
+ };
diff --git a/Documentation/devicetree/bindings/phy/renesas,usb3-phy.yaml b/Documentation/devicetree/bindings/phy/renesas,usb3-phy.yaml
new file mode 100644
index 000000000000..f459eaf55278
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/renesas,usb3-phy.yaml
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/renesas,usb3-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas R-Car generation 3 USB 3.0 PHY
+
+maintainers:
+ - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - renesas,r8a774a1-usb3-phy # RZ/G2M
+ - renesas,r8a774b1-usb3-phy # RZ/G2N
+ - renesas,r8a7795-usb3-phy # R-Car H3
+ - renesas,r8a7796-usb3-phy # R-Car M3-W
+ - renesas,r8a77961-usb3-phy # R-Car M3-W+
+ - renesas,r8a77965-usb3-phy # R-Car M3-N
+ - const: renesas,rcar-gen3-usb3-phy
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 2
+ maxItems: 3
+
+ clock-names:
+ # If you want to use the ssc, the clock-frequency of usb_extal
+ # must not be 0.
+ minItems: 2
+ maxItems: 3
+ items:
+ - const: usb3-if # The funcional clock
+ - const: usb3s_clk # The usb3's external clock
+ - const: usb_extal # The usb2's external clock
+
+ '#phy-cells':
+ # see phy-bindings.txt in the same directory
+ const: 0
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ renesas,ssc-range:
+ description: |
+ Enable/disable spread spectrum clock (ssc). 0 or the property doesn't
+ exist means disabling the ssc. The actual value will be -<value> ppm.
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - enum: [ 0, 4003, 4492, 4980 ]
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#phy-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
+ #include <dt-bindings/power/r8a7795-sysc.h>
+
+ usb-phy@e65ee000 {
+ compatible = "renesas,r8a7795-usb3-phy", "renesas,rcar-gen3-usb3-phy";
+ reg = <0xe65ee000 0x90>;
+ clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, <&usb_extal>;
+ clock-names = "usb3-if", "usb3s_clk", "usb_extal";
+ #phy-cells = <0>;
+ };