diff options
| author | Chunfeng Yun <chunfeng.yun@mediatek.com> | 2020-02-11 06:21:07 +0300 |
|---|---|---|
| committer | Kishon Vijay Abraham I <kishon@ti.com> | 2020-03-20 17:04:29 +0300 |
| commit | b51ecc0ae1fcfdb8b2fcfccfa89425f069c2771e (patch) | |
| tree | 2de1562ba3f9bbfa00c3dc73c3f265f3fed3f7b9 /Documentation/devicetree/bindings/phy | |
| parent | 6e6fed244d2d779c0cd2ae6fefc12357413c2524 (diff) | |
| download | linux-b51ecc0ae1fcfdb8b2fcfccfa89425f069c2771e.tar.xz | |
dt-bindings: phy-mtk-tphy: make the ref clock optional
Make the ref clock optional, then we no need refer to a fixed-clock
in DTS anymore when the clock of USB3 PHY comes from oscillator
directly
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Diffstat (limited to 'Documentation/devicetree/bindings/phy')
| -rw-r--r-- | Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt index ce6abfbdfbe1..1f4a36dd80e0 100644 --- a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt +++ b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt @@ -34,12 +34,6 @@ Optional properties (controller (parent) node): Required properties (port (child) node): - reg : address and length of the register set for the port. -- clocks : a list of phandle + clock-specifier pairs, one for each - entry in clock-names -- clock-names : must contain - "ref": 48M reference clock for HighSpeed analog phy; and 26M - reference clock for SuperSpeed analog phy, sometimes is - 24M, 25M or 27M, depended on platform. - #phy-cells : should be 1 (See second example) cell after port phandle is phy type from: - PHY_TYPE_USB2 @@ -48,6 +42,13 @@ Required properties (port (child) node): - PHY_TYPE_SATA Optional properties (PHY_TYPE_USB2 port (child) node): +- clocks : a list of phandle + clock-specifier pairs, one for each + entry in clock-names +- clock-names : may contain + "ref": 48M reference clock for HighSpeed anolog phy; and 26M + reference clock for SuperSpeed anolog phy, sometimes is + 24M, 25M or 27M, depended on platform. + - mediatek,eye-src : u32, the value of slew rate calibrate - mediatek,eye-vrt : u32, the selection of VRT reference voltage - mediatek,eye-term : u32, the selection of HS_TX TERM reference voltage |