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author | Yash Shah <yash.shah@sifive.com> | 2019-05-06 13:48:39 +0300 |
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committer | Palmer Dabbelt <palmer@sifive.com> | 2019-05-17 06:42:13 +0300 |
commit | 5545b6d1ba25ce4a3a339b1edb760e666e693599 (patch) | |
tree | f0578abef4b66e0aaf6ffcf087df6a2a3643183b /Documentation/devicetree/bindings/riscv | |
parent | 4c3aeb82a0f4612bf0d94fbf74c3738db2c32fe5 (diff) | |
download | linux-5545b6d1ba25ce4a3a339b1edb760e666e693599.tar.xz |
RISC-V: Add DT documentation for SiFive L2 Cache Controller
Add device tree bindings for SiFive FU540 L2 cache controller driver
Signed-off-by: Yash Shah <yash.shah@sifive.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'Documentation/devicetree/bindings/riscv')
-rw-r--r-- | Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt new file mode 100644 index 000000000000..73d8f19c3bd9 --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt @@ -0,0 +1,51 @@ +SiFive L2 Cache Controller +-------------------------- +The SiFive Level 2 Cache Controller is used to provide access to fast copies +of memory for masters in a Core Complex. The Level 2 Cache Controller also +acts as directory-based coherency manager. +All the properties in ePAPR/DeviceTree specification applies for this platform + +Required Properties: +-------------------- +- compatible: Should be "sifive,fu540-c000-ccache" and "cache" + +- cache-block-size: Specifies the block size in bytes of the cache. + Should be 64 + +- cache-level: Should be set to 2 for a level 2 cache + +- cache-sets: Specifies the number of associativity sets of the cache. + Should be 1024 + +- cache-size: Specifies the size in bytes of the cache. Should be 2097152 + +- cache-unified: Specifies the cache is a unified cache + +- interrupts: Must contain 3 entries (DirError, DataError and DataFail signals) + +- reg: Physical base address and size of L2 cache controller registers map + +Optional Properties: +-------------------- +- next-level-cache: phandle to the next level cache if present. + +- memory-region: reference to the reserved-memory for the L2 Loosely Integrated + Memory region. The reserved memory node should be defined as per the bindings + in reserved-memory.txt + + +Example: + + cache-controller@2010000 { + compatible = "sifive,fu540-c000-ccache", "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <1024>; + cache-size = <2097152>; + cache-unified; + interrupt-parent = <&plic0>; + interrupts = <1 2 3>; + reg = <0x0 0x2010000 0x0 0x1000>; + next-level-cache = <&L25 &L40 &L36>; + memory-region = <&l2_lim>; + }; |