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author | Conor Dooley <conor.dooley@microchip.com> | 2023-03-30 20:32:56 +0300 |
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committer | Rob Herring <robh@kernel.org> | 2023-04-04 20:12:13 +0300 |
commit | dc8ea9204b242cd93e63585396ac7d13f622802d (patch) | |
tree | 1073f0a5dc0669c08b65a4523185e386466aff4c /Documentation/devicetree/bindings/riscv | |
parent | 0291b586ef5df4fe9a626d01dbd53e01f8c41e3c (diff) | |
download | linux-dc8ea9204b242cd93e63585396ac7d13f622802d.tar.xz |
dt-bindings: move cache controller bindings to a cache directory
There's a bunch of bindings for (mostly l2) cache controllers
scattered to the four winds, move them to a common directory.
I renamed the freescale l2cache.txt file, as while that might make sense
when the parent dir is fsl, it's confusing after the move.
The two Marvell bindings have had a "marvell," prefix added to match
their compatibles.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230330173255.109731-1-conor@kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/riscv')
-rw-r--r-- | Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml | 170 |
1 files changed, 0 insertions, 170 deletions
diff --git a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml deleted file mode 100644 index eb6ab73c0f31..000000000000 --- a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml +++ /dev/null @@ -1,170 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) -# Copyright (C) 2020 SiFive, Inc. -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/riscv/sifive,ccache0.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: SiFive Composable Cache Controller - -maintainers: - - Paul Walmsley <paul.walmsley@sifive.com> - -description: - The SiFive Composable Cache Controller is used to provide access to fast copies - of memory for masters in a Core Complex. The Composable Cache Controller also - acts as directory-based coherency manager. - All the properties in ePAPR/DeviceTree specification applies for this platform. - -select: - properties: - compatible: - contains: - enum: - - sifive,ccache0 - - sifive,fu540-c000-ccache - - sifive,fu740-c000-ccache - - required: - - compatible - -properties: - compatible: - oneOf: - - items: - - enum: - - sifive,ccache0 - - sifive,fu540-c000-ccache - - sifive,fu740-c000-ccache - - const: cache - - items: - - const: starfive,jh7110-ccache - - const: sifive,ccache0 - - const: cache - - items: - - const: microchip,mpfs-ccache - - const: sifive,fu540-c000-ccache - - const: cache - - cache-block-size: - const: 64 - - cache-level: - enum: [2, 3] - - cache-sets: - enum: [1024, 2048] - - cache-size: - const: 2097152 - - cache-unified: true - - interrupts: - minItems: 3 - items: - - description: DirError interrupt - - description: DataError interrupt - - description: DataFail interrupt - - description: DirFail interrupt - - reg: - maxItems: 1 - - next-level-cache: true - - memory-region: - maxItems: 1 - description: | - The reference to the reserved-memory for the L2 Loosely Integrated Memory region. - The reserved memory node should be defined as per the bindings in reserved-memory.txt. - -allOf: - - $ref: /schemas/cache-controller.yaml# - - - if: - properties: - compatible: - contains: - enum: - - sifive,fu740-c000-ccache - - starfive,jh7110-ccache - - microchip,mpfs-ccache - - then: - properties: - interrupts: - description: | - Must contain entries for DirError, DataError, DataFail, DirFail signals. - minItems: 4 - - else: - properties: - interrupts: - description: | - Must contain entries for DirError, DataError and DataFail signals. - maxItems: 3 - - - if: - properties: - compatible: - contains: - enum: - - sifive,fu740-c000-ccache - - starfive,jh7110-ccache - - then: - properties: - cache-sets: - const: 2048 - - else: - properties: - cache-sets: - const: 1024 - - - if: - properties: - compatible: - contains: - const: sifive,ccache0 - - then: - properties: - cache-level: - enum: [2, 3] - - else: - properties: - cache-level: - const: 2 - -additionalProperties: false - -required: - - compatible - - cache-block-size - - cache-level - - cache-sets - - cache-size - - cache-unified - - interrupts - - reg - -examples: - - | - cache-controller@2010000 { - compatible = "sifive,fu540-c000-ccache", "cache"; - cache-block-size = <64>; - cache-level = <2>; - cache-sets = <1024>; - cache-size = <2097152>; - cache-unified; - reg = <0x2010000 0x1000>; - interrupt-parent = <&plic0>; - interrupts = <1>, - <2>, - <3>; - next-level-cache = <&L25>; - memory-region = <&l2_lim>; - }; |