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authorPeter Ujfalusi <peter.ujfalusi@ti.com>2020-06-30 15:58:42 +0300
committerMark Brown <broonie@kernel.org>2020-07-01 17:13:45 +0300
commit8142500e7dc0d214e3c7a22788116f71cd84f07b (patch)
tree3e586d956e4f2c6af8dcbd5f632515dd243f90ed /Documentation/devicetree/bindings/sound/ti,j721e-cpb-audio.yaml
parentef3ab250aad9920fa7fd6280051c92a488109b87 (diff)
downloadlinux-8142500e7dc0d214e3c7a22788116f71cd84f07b.tar.xz
ASoC: dt-bindings: Add documentation for TI j721e EVM (CPB and IVI)
The audio support on the Common Processor Board board is using pcm3168a codec connected to McASP10 serializers in parallel setup. The Infotainment board plugs into the Common Processor Board, the support of the extension board is extending the CPB audio support by adding the two codecs on the expansion board. The audio support on the Infotainment Expansion Board consists of McASP0 connected to two pcm3168a codecs with dedicated set of serializers to each. The SCKI for pcm3168a is sourced from j721e AUDIO_REFCLK0 pin. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Link: https://lore.kernel.org/r/20200630125843.11561-3-peter.ujfalusi@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
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+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/ti,j721e-cpb-audio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments J721e Common Processor Board Audio Support
+
+maintainers:
+ - Peter Ujfalusi <peter.ujfalusi@ti.com>
+
+description: |
+ The audio support on the board is using pcm3168a codec connected to McASP10
+ serializers in parallel setup.
+ The pcm3168a SCKI clock is sourced from j721e AUDIO_REFCLK2 pin.
+ In order to support 48KHz and 44.1KHz family of sampling rates the parent
+ clock for AUDIO_REFCLK2 needs to be changed between PLL4 (for 48KHz) and
+ PLL15 (for 44.1KHz). The same PLLs are used for McASP10's AUXCLK clock via
+ different HSDIVIDER.
+
+ Clocking setup for 48KHz family:
+ PLL4 ---> PLL4_HSDIV0 ---> MCASP10_AUXCLK ---> McASP10.auxclk
+ |-> PLL4_HSDIV2 ---> AUDIO_REFCLK2 ---> pcm3168a.SCKI
+
+ Clocking setup for 44.1KHz family:
+ PLL15 ---> PLL15_HSDIV0 ---> MCASP10_AUXCLK ---> McASP10.auxclk
+ |-> PLL15_HSDIV2 ---> AUDIO_REFCLK2 ---> pcm3168a.SCKI
+
+properties:
+ compatible:
+ items:
+ - const: ti,j721e-cpb-audio
+
+ model:
+ $ref: /schemas/types.yaml#/definitions/string
+ description: User specified audio sound card name
+
+ ti,cpb-mcasp:
+ description: phandle to McASP used on CPB
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/phandle
+
+ ti,cpb-codec:
+ description: phandle to the pcm3168a codec used on the CPB
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/phandle
+
+ clocks:
+ items:
+ - description: AUXCLK clock for McASP used by CPB audio
+ - description: Parent for CPB_McASP auxclk (for 48KHz)
+ - description: Parent for CPB_McASP auxclk (for 44.1KHz)
+ - description: SCKI clock for the pcm3168a codec on CPB
+ - description: Parent for CPB_SCKI clock (for 48KHz)
+ - description: Parent for CPB_SCKI clock (for 44.1KHz)
+
+ clock-names:
+ items:
+ - const: cpb-mcasp-auxclk
+ - const: cpb-mcasp-auxclk-48000
+ - const: cpb-mcasp-auxclk-44100
+ - const: cpb-codec-scki
+ - const: cpb-codec-scki-48000
+ - const: cpb-codec-scki-44100
+
+required:
+ - compatible
+ - model
+ - ti,cpb-mcasp
+ - ti,cpb-codec
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |+
+ sound {
+ compatible = "ti,j721e-cpb-audio";
+ model = "j721e-cpb";
+
+ status = "okay";
+
+ ti,cpb-mcasp = <&mcasp10>;
+ ti,cpb-codec = <&pcm3168a_1>;
+
+ clocks = <&k3_clks 184 1>,
+ <&k3_clks 184 2>, <&k3_clks 184 4>,
+ <&k3_clks 157 371>,
+ <&k3_clks 157 400>, <&k3_clks 157 401>;
+ clock-names = "cpb-mcasp-auxclk",
+ "cpb-mcasp-auxclk-48000", "cpb-mcasp-auxclk-44100",
+ "cpb-codec-scki",
+ "cpb-codec-scki-48000", "cpb-codec-scki-44100";
+ };