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authorMark Brown <broonie@opensource.wolfsonmicro.com>2013-02-11 15:06:33 +0400
committerMark Brown <broonie@opensource.wolfsonmicro.com>2013-02-11 15:06:33 +0400
commite790245eb3b437bb1d322cf3d5fbb603a138c9f7 (patch)
tree54469e8ec666cb4a03b541c218482f172b80bb24 /Documentation/devicetree/bindings/sound
parentd289323286d6b4e738458c31533da51d294d28a0 (diff)
parentfd23fb9f6bfd43a6e62b2646d18d5ca3edc3ebe3 (diff)
downloadlinux-e790245eb3b437bb1d322cf3d5fbb603a138c9f7.tar.xz
Merge remote-tracking branch 'asoc/topic/cs4271' into asoc-next
Diffstat (limited to 'Documentation/devicetree/bindings/sound')
-rw-r--r--Documentation/devicetree/bindings/sound/cs4271.txt12
1 files changed, 12 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/sound/cs4271.txt b/Documentation/devicetree/bindings/sound/cs4271.txt
index a850fb9c88ea..e2cd1d7539e5 100644
--- a/Documentation/devicetree/bindings/sound/cs4271.txt
+++ b/Documentation/devicetree/bindings/sound/cs4271.txt
@@ -20,6 +20,18 @@ Optional properties:
!RESET pin
- cirrus,amuteb-eq-bmutec: When given, the Codec's AMUTEB=BMUTEC flag
is enabled.
+ - cirrus,enable-soft-reset:
+ The CS4271 requires its LRCLK and MCLK to be stable before its RESET
+ line is de-asserted. That also means that clocks cannot be changed
+ without putting the chip back into hardware reset, which also requires
+ a complete re-initialization of all registers.
+
+ One (undocumented) workaround is to assert and de-assert the PDN bit
+ in the MODE2 register. This workaround can be enabled with this DT
+ property.
+
+ Note that this is not needed in case the clocks are stable
+ throughout the entire runtime of the codec.
Examples: