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author | Anson Huang <Anson.Huang@nxp.com> | 2020-04-21 17:21:26 +0300 |
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committer | Rob Herring <robh@kernel.org> | 2020-05-11 21:59:59 +0300 |
commit | 8d99f03c9fd0cf1b07821bb3caf6e3e82fe99646 (patch) | |
tree | 91c9b9b8ab9e564a2dc216e61827eb8e39221560 /Documentation/devicetree/bindings/watchdog | |
parent | 81e41fec803da7f22401fb4b2e7b61291dff8cf9 (diff) | |
download | linux-8d99f03c9fd0cf1b07821bb3caf6e3e82fe99646.tar.xz |
dt-bindings: watchdog: Convert i.MX7ULP to json-schema
Convert the i.MX7ULP watchdog binding to DT schema format using json-schema.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/watchdog')
-rw-r--r-- | Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.txt | 22 | ||||
-rw-r--r-- | Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.yaml | 60 |
2 files changed, 60 insertions, 22 deletions
diff --git a/Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.txt b/Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.txt deleted file mode 100644 index f902508d6cac..000000000000 --- a/Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.txt +++ /dev/null @@ -1,22 +0,0 @@ -* Freescale i.MX7ULP Watchdog Timer (WDT) Controller - -Required properties: -- compatible : Should be "fsl,imx7ulp-wdt" -- reg : Should contain WDT registers location and length -- interrupts : Should contain WDT interrupt -- clocks: Should contain a phandle pointing to the gated peripheral clock. - -Optional properties: -- timeout-sec : Contains the watchdog timeout in seconds - -Examples: - -wdog1: watchdog@403d0000 { - compatible = "fsl,imx7ulp-wdt"; - reg = <0x403d0000 0x10000>; - interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pcc2 IMX7ULP_CLK_WDG1>; - assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>; - assigned-clocks-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>; - timeout-sec = <40>; -}; diff --git a/Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.yaml b/Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.yaml new file mode 100644 index 000000000000..51d6d482bbc2 --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/fsl-imx7ulp-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX7ULP Watchdog Timer (WDT) Controller + +maintainers: + - Anson Huang <Anson.Huang@nxp.com> + +allOf: + - $ref: "watchdog.yaml#" + +properties: + compatible: + enum: + - fsl,imx7ulp-wdt + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + assigned-clocks: + maxItems: 1 + + assigned-clocks-parents: + maxItems: 1 + + timeout-sec: true + +required: + - compatible + - interrupts + - reg + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/imx7ulp-clock.h> + + watchdog@403d0000 { + compatible = "fsl,imx7ulp-wdt"; + reg = <0x403d0000 0x10000>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pcc2 IMX7ULP_CLK_WDG1>; + assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>; + assigned-clocks-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>; + timeout-sec = <40>; + }; + +... |