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authorLinus Torvalds <torvalds@linux-foundation.org>2024-01-17 21:50:46 +0300
committerLinus Torvalds <torvalds@linux-foundation.org>2024-01-17 21:50:46 +0300
commit4331f070267ae8f76db1abbc7f4eeed4f06ae817 (patch)
treea17dc8034c988daef4e2070ebf1ea5b30bad7770 /Documentation/devicetree
parent6cff79f4b90a42d73f039564f09fa5d59ec3d8ab (diff)
parentcb51bfee7f62a8e26b694f9d84c0041b3e3ccc71 (diff)
downloadlinux-4331f070267ae8f76db1abbc7f4eeed4f06ae817.tar.xz
Merge tag 'riscv-for-linus-6.8-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull RISC-V updates from Palmer Dabbelt: - Support for many new extensions in hwprobe, along with a handful of cleanups - Various cleanups to our page table handling code, so we alwayse use {READ,WRITE}_ONCE - Support for the which-cpus flavor of hwprobe - Support for XIP kernels has been resurrected * tag 'riscv-for-linus-6.8-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (52 commits) riscv: hwprobe: export Zicond extension riscv: hwprobe: export Zacas ISA extension riscv: add ISA extension parsing for Zacas dt-bindings: riscv: add Zacas ISA extension description riscv: hwprobe: export Ztso ISA extension riscv: add ISA extension parsing for Ztso use linux/export.h rather than asm-generic/export.h riscv: Remove SHADOW_OVERFLOW_STACK_SIZE macro riscv; fix __user annotation in save_v_state() riscv: fix __user annotation in traps_misaligned.c riscv: Select ARCH_WANTS_NO_INSTR riscv: Remove obsolete rv32_defconfig file riscv: Allow disabling of BUILTIN_DTB for XIP riscv: Fixed wrong register in XIP_FIXUP_FLASH_OFFSET macro riscv: Make XIP bootable again riscv: Fix set_direct_map_default_noflush() to reset _PAGE_EXEC riscv: Fix module_alloc() that did not reset the linear mapping permissions riscv: Fix wrong usage of lm_alias() when splitting a huge linear mapping riscv: Check if the code to patch lies in the exit section riscv: Use the same CPU operations for all CPUs ...
Diffstat (limited to 'Documentation/devicetree')
-rw-r--r--Documentation/devicetree/bindings/riscv/cpus.yaml1
-rw-r--r--Documentation/devicetree/bindings/riscv/extensions.yaml219
2 files changed, 220 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index f392e367d673..23646b684ea2 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -32,6 +32,7 @@ properties:
oneOf:
- items:
- enum:
+ - amd,mbv32
- andestech,ax45mp
- canaan,k210
- sifive,bullet0
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index c91ab0e46648..27beedb98198 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -171,6 +171,12 @@ properties:
memory types as ratified in the 20191213 version of the privileged
ISA specification.
+ - const: zacas
+ description: |
+ The Zacas extension for Atomic Compare-and-Swap (CAS) instructions
+ is supported as ratified at commit 5059e0ca641c ("update to
+ ratified") of the riscv-zacas.
+
- const: zba
description: |
The standard Zba bit-manipulation extension for address generation
@@ -190,12 +196,111 @@ properties:
multiplication as ratified at commit 6d33919 ("Merge pull request
#158 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.
+ - const: zbkb
+ description:
+ The standard Zbkb bitmanip instructions for cryptography as ratified
+ in version 1.0 of RISC-V Cryptography Extensions Volume I
+ specification.
+
+ - const: zbkc
+ description:
+ The standard Zbkc carry-less multiply instructions as ratified
+ in version 1.0 of RISC-V Cryptography Extensions Volume I
+ specification.
+
+ - const: zbkx
+ description:
+ The standard Zbkx crossbar permutation instructions as ratified
+ in version 1.0 of RISC-V Cryptography Extensions Volume I
+ specification.
+
- const: zbs
description: |
The standard Zbs bit-manipulation extension for single-bit
instructions as ratified at commit 6d33919 ("Merge pull request #158
from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.
+ - const: zfa
+ description:
+ The standard Zfa extension for additional floating point
+ instructions, as ratified in commit 056b6ff ("Zfa is ratified") of
+ riscv-isa-manual.
+
+ - const: zfh
+ description:
+ The standard Zfh extension for 16-bit half-precision binary
+ floating-point instructions, as ratified in commit 64074bc ("Update
+ version numbers for Zfh/Zfinx") of riscv-isa-manual.
+
+ - const: zfhmin
+ description:
+ The standard Zfhmin extension which provides minimal support for
+ 16-bit half-precision binary floating-point instructions, as ratified
+ in commit 64074bc ("Update version numbers for Zfh/Zfinx") of
+ riscv-isa-manual.
+
+ - const: zk
+ description:
+ The standard Zk Standard Scalar cryptography extension as ratified
+ in version 1.0 of RISC-V Cryptography Extensions Volume I
+ specification.
+
+ - const: zkn
+ description:
+ The standard Zkn NIST algorithm suite extensions as ratified in
+ version 1.0 of RISC-V Cryptography Extensions Volume I
+ specification.
+
+ - const: zknd
+ description: |
+ The standard Zknd for NIST suite: AES decryption instructions as
+ ratified in version 1.0 of RISC-V Cryptography Extensions Volume I
+ specification.
+
+ - const: zkne
+ description: |
+ The standard Zkne for NIST suite: AES encryption instructions as
+ ratified in version 1.0 of RISC-V Cryptography Extensions Volume I
+ specification.
+
+ - const: zknh
+ description: |
+ The standard Zknh for NIST suite: hash function instructions as
+ ratified in version 1.0 of RISC-V Cryptography Extensions Volume I
+ specification.
+
+ - const: zkr
+ description:
+ The standard Zkr entropy source extension as ratified in version
+ 1.0 of RISC-V Cryptography Extensions Volume I specification.
+ This string being present means that the CSR associated to this
+ extension is accessible at the privilege level to which that
+ device-tree has been provided.
+
+ - const: zks
+ description:
+ The standard Zks ShangMi algorithm suite extensions as ratified in
+ version 1.0 of RISC-V Cryptography Extensions Volume I
+ specification.
+
+ - const: zksed
+ description: |
+ The standard Zksed for ShangMi suite: SM4 block cipher instructions
+ as ratified in version 1.0 of RISC-V Cryptography Extensions
+ Volume I specification.
+
+ - const: zksh
+ description: |
+ The standard Zksh for ShangMi suite: SM3 hash function instructions
+ as ratified in version 1.0 of RISC-V Cryptography Extensions
+ Volume I specification.
+
+ - const: zkt
+ description:
+ The standard Zkt for data independent execution latency as ratified
+ in version 1.0 of RISC-V Cryptography Extensions Volume I
+ specification.
+
- const: zicbom
description:
The standard Zicbom extension for base cache management operations as
@@ -246,6 +351,12 @@ properties:
The standard Zihintpause extension for pause hints, as ratified in
commit d8ab5c7 ("Zihintpause is ratified") of the riscv-isa-manual.
+ - const: zihintntl
+ description:
+ The standard Zihintntl extension for non-temporal locality hints, as
+ ratified in commit 0dc91f5 ("Zihintntl is ratified") of the
+ riscv-isa-manual.
+
- const: zihpm
description:
The standard Zihpm extension for hardware performance counters, as
@@ -258,5 +369,113 @@ properties:
in commit 2e5236 ("Ztso is now ratified.") of the
riscv-isa-manual.
+ - const: zvbb
+ description:
+ The standard Zvbb extension for vectored basic bit-manipulation
+ instructions, as ratified in commit 56ed795 ("Update
+ riscv-crypto-spec-vector.adoc") of riscv-crypto.
+
+ - const: zvbc
+ description:
+ The standard Zvbc extension for vectored carryless multiplication
+ instructions, as ratified in commit 56ed795 ("Update
+ riscv-crypto-spec-vector.adoc") of riscv-crypto.
+
+ - const: zvfh
+ description:
+ The standard Zvfh extension for vectored half-precision
+ floating-point instructions, as ratified in commit e2ccd05
+ ("Remove draft warnings from Zvfh[min]") of riscv-v-spec.
+
+ - const: zvfhmin
+ description:
+ The standard Zvfhmin extension for vectored minimal half-precision
+ floating-point instructions, as ratified in commit e2ccd05
+ ("Remove draft warnings from Zvfh[min]") of riscv-v-spec.
+
+ - const: zvkb
+ description:
+ The standard Zvkb extension for vector cryptography bit-manipulation
+ instructions, as ratified in commit 56ed795 ("Update
+ riscv-crypto-spec-vector.adoc") of riscv-crypto.
+
+ - const: zvkg
+ description:
+ The standard Zvkg extension for vector GCM/GMAC instructions, as
+ ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc")
+ of riscv-crypto.
+
+ - const: zvkn
+ description:
+ The standard Zvkn extension for NIST algorithm suite instructions, as
+ ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc")
+ of riscv-crypto.
+
+ - const: zvknc
+ description:
+ The standard Zvknc extension for NIST algorithm suite with carryless
+ multiply instructions, as ratified in commit 56ed795 ("Update
+ riscv-crypto-spec-vector.adoc") of riscv-crypto.
+
+ - const: zvkned
+ description:
+ The standard Zvkned extension for Vector AES block cipher
+ instructions, as ratified in commit 56ed795 ("Update
+ riscv-crypto-spec-vector.adoc") of riscv-crypto.
+
+ - const: zvkng
+ description:
+ The standard Zvkng extension for NIST algorithm suite with GCM
+ instructions, as ratified in commit 56ed795 ("Update
+ riscv-crypto-spec-vector.adoc") of riscv-crypto.
+
+ - const: zvknha
+ description: |
+ The standard Zvknha extension for NIST suite: vector SHA-2 secure,
+ hash (SHA-256 only) instructions, as ratified in commit
+ 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto.
+
+ - const: zvknhb
+ description: |
+ The standard Zvknhb extension for NIST suite: vector SHA-2 secure,
+ hash (SHA-256 and SHA-512) instructions, as ratified in commit
+ 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto.
+
+ - const: zvks
+ description:
+ The standard Zvks extension for ShangMi algorithm suite
+ instructions, as ratified in commit 56ed795 ("Update
+ riscv-crypto-spec-vector.adoc") of riscv-crypto.
+
+ - const: zvksc
+ description:
+ The standard Zvksc extension for ShangMi algorithm suite with
+ carryless multiplication instructions, as ratified in commit 56ed795
+ ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto.
+
+ - const: zvksed
+ description: |
+ The standard Zvksed extension for ShangMi suite: SM4 block cipher
+ instructions, as ratified in commit 56ed795 ("Update
+ riscv-crypto-spec-vector.adoc") of riscv-crypto.
+
+ - const: zvksh
+ description: |
+ The standard Zvksh extension for ShangMi suite: SM3 secure hash
+ instructions, as ratified in commit 56ed795 ("Update
+ riscv-crypto-spec-vector.adoc") of riscv-crypto.
+
+ - const: zvksg
+ description:
+ The standard Zvksg extension for ShangMi algorithm suite with GCM
+ instructions, as ratified in commit 56ed795 ("Update
+ riscv-crypto-spec-vector.adoc") of riscv-crypto.
+
+ - const: zvkt
+ description:
+ The standard Zvkt extension for vector data-independent execution
+ latency, as ratified in commit 56ed795 ("Update
+ riscv-crypto-spec-vector.adoc") of riscv-crypto.
+
additionalProperties: true
...