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authorLinus Torvalds <torvalds@linux-foundation.org>2022-08-01 22:37:54 +0300
committerLinus Torvalds <torvalds@linux-foundation.org>2022-08-01 22:37:54 +0300
commitdfea84827f7eb49ca41d837d92ac1cbd5353a742 (patch)
tree2d7312288f16b0effadafb5db5218553ea7c61f8 /Documentation/devicetree
parent63e6053add5a6cec4dbfa3dec12e0d4439daac4a (diff)
parentcceeeb6a6d02e7b9a74ddd27a3225013b34174aa (diff)
downloadlinux-dfea84827f7eb49ca41d837d92ac1cbd5353a742.tar.xz
Merge tag 'timers-core-2022-08-01' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull timer updates from Thomas Gleixner: "Timers, timekeeping and related drivers update: Core: - Make wait_event_hrtimeout() aware of RT/DL tasks New drivers: - R-Car Gen4 timer - Tegra186 timer - Mediatek MT6795 CPUXGPT timer Updates: - Rework suspend/resume handling in timer drivers so it takes inactive clocks into account. - The usual device tree compatible add ons - Small fixed and cleanups all over the place" * tag 'timers-core-2022-08-01' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (24 commits) wait: Fix __wait_event_hrtimeout for RT/DL tasks clocksource/drivers/sun5i: Remove unnecessary (void*) conversions dt-bindings: timer: allwinner,sun4i-a10-timer: Add D1 compatible dt-bindings: timer: ingenic,tcu: use absolute path to other schema clocksource/drivers/sun4i: Remove unnecessary (void*) conversions dt-bindings: timer: renesas,cmt: Fix R-Car Gen4 fall-out clocksource/drivers/tegra186: Put Kconfig option 'tristate' to 'bool' clocksource/drivers/timer-ti-dm: Make driver selection bool for TI K3 clocksource/drivers/timer-ti-dm: Add compatible for am6 SoCs clocksource/drivers/timer-ti-dm: Make timer selectable for ARCH_K3 clocksource/drivers/timer-ti-dm: Move inline functions to driver for am6 clocksource/drivers/sh_cmt: Add R-Car Gen4 support dt-bindings: timer: renesas,cmt: R-Car V3U is R-Car Gen4 dt-bindings: timer: renesas,cmt: Add r8a779f0 and generic Gen4 CMT support clocksource/drivers/timer-microchip-pit64b: Fix compilation warnings clocksource/drivers/timer-microchip-pit64b: Use mchp_pit64b_{suspend, resume} clocksource/drivers/timer-microchip-pit64b: Remove suspend/resume ops for ce thermal/drivers/rcar_gen3_thermal: Add r8a779f0 support clocksource/drivers/timer-mediatek: Implement CPUXGPT timers dt-bindings: timer: mediatek: Add CPUX System Timer and MT6795 compatible ...
Diffstat (limited to 'Documentation/devicetree')
-rw-r--r--Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml1
-rw-r--r--Documentation/devicetree/bindings/timer/ingenic,tcu.yaml4
-rw-r--r--Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt6
-rw-r--r--Documentation/devicetree/bindings/timer/renesas,cmt.yaml16
-rw-r--r--Documentation/devicetree/bindings/timer/st,nomadik-mtu.yaml58
5 files changed, 80 insertions, 5 deletions
diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml b/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml
index 53fd24bdc34e..3711872b6b99 100644
--- a/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml
+++ b/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml
@@ -20,6 +20,7 @@ properties:
- allwinner,suniv-f1c100s-timer
- items:
- enum:
+ - allwinner,sun20i-d1-timer
- allwinner,sun50i-a64-timer
- allwinner,sun50i-h6-timer
- allwinner,sun50i-h616-timer
diff --git a/Documentation/devicetree/bindings/timer/ingenic,tcu.yaml b/Documentation/devicetree/bindings/timer/ingenic,tcu.yaml
index d541cf2067bc..0a01e4f5eddb 100644
--- a/Documentation/devicetree/bindings/timer/ingenic,tcu.yaml
+++ b/Documentation/devicetree/bindings/timer/ingenic,tcu.yaml
@@ -113,7 +113,7 @@ properties:
patternProperties:
"^watchdog@[a-f0-9]+$":
type: object
- $ref: ../watchdog/watchdog.yaml#
+ $ref: /schemas/watchdog/watchdog.yaml#
properties:
compatible:
oneOf:
@@ -145,7 +145,7 @@ patternProperties:
"^pwm@[a-f0-9]+$":
type: object
- $ref: ../pwm/pwm.yaml#
+ $ref: /schemas/pwm/pwm.yaml#
properties:
compatible:
oneOf:
diff --git a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
index 6f1f9dba6e88..f1c848af91d3 100644
--- a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
+++ b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
@@ -1,7 +1,8 @@
MediaTek Timers
---------------
-MediaTek SoCs have two different timers on different platforms,
+MediaTek SoCs have different timers on different platforms,
+- CPUX (ARM/ARM64 System Timer)
- GPT (General Purpose Timer)
- SYST (System Timer)
@@ -29,6 +30,9 @@ Required properties:
* "mediatek,mt7629-timer" for MT7629 compatible timers (SYST)
* "mediatek,mt6765-timer" for MT6765 and all above compatible timers (SYST)
+ For those SoCs that use CPUX
+ * "mediatek,mt6795-systimer" for MT6795 compatible timers (CPUX)
+
- reg: Should contain location and length for timer register.
- clocks: Should contain system clock.
diff --git a/Documentation/devicetree/bindings/timer/renesas,cmt.yaml b/Documentation/devicetree/bindings/timer/renesas,cmt.yaml
index 53dd6d9f518f..bde6c9b66bf4 100644
--- a/Documentation/devicetree/bindings/timer/renesas,cmt.yaml
+++ b/Documentation/devicetree/bindings/timer/renesas,cmt.yaml
@@ -80,7 +80,6 @@ properties:
- renesas,r8a77980-cmt0 # 32-bit CMT0 on R-Car V3H
- renesas,r8a77990-cmt0 # 32-bit CMT0 on R-Car E3
- renesas,r8a77995-cmt0 # 32-bit CMT0 on R-Car D3
- - renesas,r8a779a0-cmt0 # 32-bit CMT0 on R-Car V3U
- const: renesas,rcar-gen3-cmt0 # 32-bit CMT0 on R-Car Gen3 and RZ/G2
- items:
@@ -97,9 +96,20 @@ properties:
- renesas,r8a77980-cmt1 # 48-bit CMT on R-Car V3H
- renesas,r8a77990-cmt1 # 48-bit CMT on R-Car E3
- renesas,r8a77995-cmt1 # 48-bit CMT on R-Car D3
- - renesas,r8a779a0-cmt1 # 48-bit CMT on R-Car V3U
- const: renesas,rcar-gen3-cmt1 # 48-bit CMT on R-Car Gen3 and RZ/G2
+ - items:
+ - enum:
+ - renesas,r8a779a0-cmt0 # 32-bit CMT0 on R-Car V3U
+ - renesas,r8a779f0-cmt0 # 32-bit CMT0 on R-Car S4-8
+ - const: renesas,rcar-gen4-cmt0 # 32-bit CMT0 on R-Car Gen4
+
+ - items:
+ - enum:
+ - renesas,r8a779a0-cmt1 # 48-bit CMT on R-Car V3U
+ - renesas,r8a779f0-cmt1 # 48-bit CMT on R-Car S4-8
+ - const: renesas,rcar-gen4-cmt1 # 48-bit CMT on R-Car Gen4
+
reg:
maxItems: 1
@@ -135,6 +145,7 @@ allOf:
enum:
- renesas,rcar-gen2-cmt0
- renesas,rcar-gen3-cmt0
+ - renesas,rcar-gen4-cmt0
then:
properties:
interrupts:
@@ -148,6 +159,7 @@ allOf:
enum:
- renesas,rcar-gen2-cmt1
- renesas,rcar-gen3-cmt1
+ - renesas,rcar-gen4-cmt1
then:
properties:
interrupts:
diff --git a/Documentation/devicetree/bindings/timer/st,nomadik-mtu.yaml b/Documentation/devicetree/bindings/timer/st,nomadik-mtu.yaml
new file mode 100644
index 000000000000..901848d298ec
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/st,nomadik-mtu.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2022 Linaro Ltd.
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/timer/st,nomadik-mtu.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: ST Microelectronics Nomadik Multi-Timer Unit MTU Timer
+
+maintainers:
+ - Linus Walleij <linus.walleij@linaro.org>
+
+description: This timer is found in the ST Microelectronics Nomadik
+ SoCs STn8800, STn8810 and STn8815 as well as in ST-Ericsson DB8500.
+
+properties:
+ compatible:
+ items:
+ - const: st,nomadik-mtu
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ description: The first clock named TIMCLK clocks the actual timers and
+ the second clock clocks the digital interface to the interconnect.
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: timclk
+ - const: apb_pclk
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/mfd/dbx500-prcmu.h>
+ timer@a03c6000 {
+ compatible = "st,nomadik-mtu";
+ reg = <0xa03c6000 0x1000>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&prcmu_clk PRCMU_TIMCLK>, <&prcc_pclk 6 6>;
+ clock-names = "timclk", "apb_pclk";
+ };