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author | Paolo Abeni <pabeni@redhat.com> | 2023-09-14 20:48:23 +0300 |
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committer | Paolo Abeni <pabeni@redhat.com> | 2023-09-14 20:48:23 +0300 |
commit | f2fa1c812c91e99d0317d1fc7d845e1e05f39716 (patch) | |
tree | 8253727a8947e8b63a5c9b504d0bfb735648471b /Documentation/devicetree | |
parent | 59bb1d698028d7f01650f9def579efdfdfb7039f (diff) | |
parent | 9fdfb15a3dbf818e06be514f4abbfc071004cbe7 (diff) | |
download | linux-f2fa1c812c91e99d0317d1fc7d845e1e05f39716.tar.xz |
Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
Cross-merge networking fixes after downstream PR.
No conflicts.
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
Diffstat (limited to 'Documentation/devicetree')
-rw-r--r-- | Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml | 81 | ||||
-rw-r--r-- | Documentation/devicetree/bindings/sound/fsl,easrc.yaml | 8 |
2 files changed, 88 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml new file mode 100644 index 000000000000..9ab5f0c435d4 --- /dev/null +++ b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright (C) 2023 Renesas Electronics Corp. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cache/andestech,ax45mp-cache.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Andestech AX45MP L2 Cache Controller + +maintainers: + - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> + +description: + A level-2 cache (L2C) is used to improve the system performance by providing + a large amount of cache line entries and reasonable access delays. The L2C + is shared between cores, and a non-inclusive non-exclusive policy is used. + +select: + properties: + compatible: + contains: + enum: + - andestech,ax45mp-cache + + required: + - compatible + +properties: + compatible: + items: + - const: andestech,ax45mp-cache + - const: cache + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + cache-line-size: + const: 64 + + cache-level: + const: 2 + + cache-sets: + const: 1024 + + cache-size: + enum: [131072, 262144, 524288, 1048576, 2097152] + + cache-unified: true + + next-level-cache: true + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + - cache-line-size + - cache-level + - cache-sets + - cache-size + - cache-unified + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + cache-controller@2010000 { + compatible = "andestech,ax45mp-cache", "cache"; + reg = <0x13400000 0x100000>; + interrupts = <508 IRQ_TYPE_LEVEL_HIGH>; + cache-line-size = <64>; + cache-level = <2>; + cache-sets = <1024>; + cache-size = <262144>; + cache-unified; + }; diff --git a/Documentation/devicetree/bindings/sound/fsl,easrc.yaml b/Documentation/devicetree/bindings/sound/fsl,easrc.yaml index bdde68a1059c..a680d7aff237 100644 --- a/Documentation/devicetree/bindings/sound/fsl,easrc.yaml +++ b/Documentation/devicetree/bindings/sound/fsl,easrc.yaml @@ -14,7 +14,13 @@ properties: pattern: "^easrc@.*" compatible: - const: fsl,imx8mn-easrc + oneOf: + - enum: + - fsl,imx8mn-easrc + - items: + - enum: + - fsl,imx8mp-easrc + - const: fsl,imx8mn-easrc reg: maxItems: 1 |