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authorMauro Carvalho Chehab <mchehab+huawei@kernel.org>2020-09-29 12:09:46 +0300
committerMauro Carvalho Chehab <mchehab+huawei@kernel.org>2020-10-15 08:49:43 +0300
commit64d4151658c14b18905ba0d82cc26ccf6b92a1a1 (patch)
treeeacc43a02026c928452a7784e9fbafac52c5246e /Documentation/driver-api/fpga/fpga-programming.rst
parent4d9d18ad669170eb97606bcbe832517495737c57 (diff)
downloadlinux-64d4151658c14b18905ba0d82cc26ccf6b92a1a1.tar.xz
docs: fpga: replace :c:member: macros
Those macros are not doing the right thing with Sphinx 3, causing parse errors: ./Documentation/driver-api/fpga/fpga-mgr.rst:104: WARNING: Unparseable C cross-reference: 'fpga_manager->state' Invalid C declaration: Expected end of definition. [error at 12] fpga_manager->state ------------^ ./Documentation/driver-api/fpga/fpga-programming.rst:18: WARNING: Unparseable C cross-reference: 'fpga_region->info' Invalid C declaration: Expected end of definition. [error at 11] fpga_region->info -----------^ ./Documentation/driver-api/fpga/fpga-region.rst:62: WARNING: Unparseable C cross-reference: 'fpga_region->bridge_list' Invalid C declaration: Expected end of definition. [error at 11] fpga_region->bridge_list -----------^ ./Documentation/driver-api/fpga/fpga-region.rst:62: WARNING: Unparseable C cross-reference: 'fpga_region->get_bridges' Invalid C declaration: Expected end of definition. [error at 11] fpga_region->get_bridges -----------^ Replace them by :c:expr:, with does what's desired. Reviewed-by: Moritz Fischer <mdf@kernel.org> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Diffstat (limited to 'Documentation/driver-api/fpga/fpga-programming.rst')
-rw-r--r--Documentation/driver-api/fpga/fpga-programming.rst2
1 files changed, 1 insertions, 1 deletions
diff --git a/Documentation/driver-api/fpga/fpga-programming.rst b/Documentation/driver-api/fpga/fpga-programming.rst
index f487ad64dfb9..002392dab04f 100644
--- a/Documentation/driver-api/fpga/fpga-programming.rst
+++ b/Documentation/driver-api/fpga/fpga-programming.rst
@@ -15,7 +15,7 @@ the FPGA manager and bridges. It will:
* lock the mutex of the region's FPGA manager
* build a list of FPGA bridges if a method has been specified to do so
* disable the bridges
- * program the FPGA using info passed in :c:member:`fpga_region->info`.
+ * program the FPGA using info passed in :c:expr:`fpga_region->info`.
* re-enable the bridges
* release the locks