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authorLinus Torvalds <torvalds@linux-foundation.org>2019-09-20 00:19:33 +0300
committerLinus Torvalds <torvalds@linux-foundation.org>2019-09-20 00:19:33 +0300
commit3c2edc36a77420d8be05d656019dbc8c31535992 (patch)
tree70d8c9abb04c89e82c79c46efd2f7cb1bf836ef5 /Documentation/driver-api
parent32b90daf5cafdda62b1ce62d0b7445fa9107babf (diff)
parentcb0438e4436085d89706b5ccfce4d5da531253de (diff)
downloadlinux-3c2edc36a77420d8be05d656019dbc8c31535992.tar.xz
Merge tag 'pinctrl-v5.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for the v5.4 kernel cycle: Core changes: - Fix errors in example code in the documentation. New drivers: - Add support for JZ4760, JZ4760B, X1000, X1000E and X1500 to the Ingenic driver. - Support Cirrus Logic Madera CS47L92 and CS47L15. - Support Allwinner Sunxi V3S. - Support Aspeed 2600 BMC. - Support Qualcomm SC7180. - Support Marvell MVEBU CS115. Driver improvements: - Clean up a few drivers to use the devm_platform_ioremap_resource() helper. - Pass the irqchip when registering the gpio_chip in some pin controllers that are also GPIO controllers. - Support suspend/resume in the Tegra driver. - Support pull-up on the Broadcom BCM2711. - The Intel driver can now request locked pads. - Fix the UFS reset pin in the Qualcomm SDM845 driver" * tag 'pinctrl-v5.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (112 commits) pinctrl: meson-gxbb: Fix wrong pinning definition for uart_c pinctrl: sh-pfc: Unlock on error in sh_pfc_func_set_mux() pinctrl: bcm: remove redundant assignment to pointer log pinctrl: iproc: Add 'get_direction' support pinctrl: iproc-gpio: Handle interrupts for multiple instances pinctrl: iproc-gpio: Fix incorrect pinconf configurations pinctrl: intel: mark intel_pin_to_gpio __maybe_unused pinctrl: qcom: sdm845: Fix UFS_RESET pin pinctrl: mvebu: add additional variant for standalone CP115 pinctrl: mvebu: Add CP110 missing pin functionality dt-bindings: cp110: document the new CP115 pinctrl compatible pinctrl: bcm2835: Pass irqchip when adding gpiochip pinctrl: meson: meson: Add of_node_put() before return pinctrl/gpio: Take MUX usage into account dt-bindings: pinctrl: qcom-pmic-gpio: Add pm8150l support dt-bindings: pinctrl: qcom-pmic-gpio: Add pm8150b support dt-bindings: pinctrl: qcom-pmic-gpio: Add pm8150 support pinctrl: amd: disable spurious-firing GPIO IRQs pinctrl: rza2: Include the appropriate headers pinctrl: rza2: Drop driver use of consumer flags ...
Diffstat (limited to 'Documentation/driver-api')
-rw-r--r--Documentation/driver-api/pinctl.rst6
1 files changed, 3 insertions, 3 deletions
diff --git a/Documentation/driver-api/pinctl.rst b/Documentation/driver-api/pinctl.rst
index 2bb1bc484278..3d2deaf48841 100644
--- a/Documentation/driver-api/pinctl.rst
+++ b/Documentation/driver-api/pinctl.rst
@@ -638,8 +638,8 @@ group of pins would work something like this::
}
static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
- unsigned ** const pins,
- unsigned * const num_pins)
+ const unsigned ** pins,
+ unsigned * num_pins)
{
*pins = (unsigned *) foo_groups[selector].pins;
*num_pins = foo_groups[selector].num_pins;
@@ -705,7 +705,7 @@ group of pins would work something like this::
{
u8 regbit = (1 << selector + group);
- writeb((readb(MUX)|regbit), MUX)
+ writeb((readb(MUX)|regbit), MUX);
return 0;
}