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authorZong Li <zong.li@sifive.com>2020-01-02 06:09:54 +0300
committerPaul Walmsley <paul.walmsley@sifive.com>2020-01-03 11:47:02 +0300
commit0da310e82d3a9bff6ef6b0f2fbf45d1a05cc64fe (patch)
treef8e5eeb96d120146213c3421f7f05b65b67f8dd2 /Documentation/features/debug
parentac51e005fe1456a288929a41d71adc6224e912d2 (diff)
downloadlinux-0da310e82d3a9bff6ef6b0f2fbf45d1a05cc64fe.tar.xz
riscv: gcov: enable gcov for RISC-V
This patch enables GCOV code coverage measurement on RISC-V. Lightly tested on QEMU and Hifive Unleashed board, seems to work as expected. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Acked-by: Jonathan Corbet <corbet@lwn.net> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
Diffstat (limited to 'Documentation/features/debug')
-rw-r--r--Documentation/features/debug/gcov-profile-all/arch-support.txt2
1 files changed, 1 insertions, 1 deletions
diff --git a/Documentation/features/debug/gcov-profile-all/arch-support.txt b/Documentation/features/debug/gcov-profile-all/arch-support.txt
index 059d58a549c7..6fb2b0671994 100644
--- a/Documentation/features/debug/gcov-profile-all/arch-support.txt
+++ b/Documentation/features/debug/gcov-profile-all/arch-support.txt
@@ -23,7 +23,7 @@
| openrisc: | TODO |
| parisc: | TODO |
| powerpc: | ok |
- | riscv: | TODO |
+ | riscv: | ok |
| s390: | ok |
| sh: | ok |
| sparc: | TODO |