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| author | Huacai Chen <chenhuacai@loongson.cn> | 2022-05-31 13:04:10 +0300 |
|---|---|---|
| committer | Huacai Chen <chenhuacai@loongson.cn> | 2022-06-03 15:09:27 +0300 |
| commit | 0ea8ce61cb2c487e818c515f91329fa9972a7155 (patch) | |
| tree | 02f569d9eb1220d822870300ec918d44b82ec22b /Documentation/loongarch/index.rst | |
| parent | fa84f89395e0383b94ae2822003d8940fdb24d3c (diff) | |
| download | linux-0ea8ce61cb2c487e818c515f91329fa9972a7155.tar.xz | |
Documentation: LoongArch: Add basic documentations
Add some basic documentation for LoongArch. LoongArch is a new RISC ISA,
which is a bit like MIPS or RISC-V. LoongArch includes a reduced 32-bit
version (LA32R), a standard 32-bit version (LA32S) and a 64-bit version
(LA64).
Tested-by: Bagas Sanjaya <bagasdotme@gmail.com>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Co-developed-by: WANG Xuerui <git@xen0n.name>
Signed-off-by: WANG Xuerui <git@xen0n.name>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
Diffstat (limited to 'Documentation/loongarch/index.rst')
| -rw-r--r-- | Documentation/loongarch/index.rst | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/Documentation/loongarch/index.rst b/Documentation/loongarch/index.rst new file mode 100644 index 000000000000..aaba648db907 --- /dev/null +++ b/Documentation/loongarch/index.rst @@ -0,0 +1,21 @@ +.. SPDX-License-Identifier: GPL-2.0 + +====================== +LoongArch Architecture +====================== + +.. toctree:: + :maxdepth: 2 + :numbered: + + introduction + irq-chip-model + + features + +.. only:: subproject and html + + Indices + ======= + + * :ref:`genindex` |