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authorGiuseppe CAVALLARO <peppe.cavallaro@st.com>2012-04-04 08:33:27 +0400
committerDavid S. Miller <davem@davemloft.net>2012-04-05 02:39:24 +0400
commitcd7201f477b965f6c0220b798813c7000bc603c5 (patch)
tree0b5ac87d64a90efc1ddfca8620019c13fd0acad8 /Documentation/networking
parent18f05d64ec36e27892cc0f55be707762aae053a1 (diff)
downloadlinux-cd7201f477b965f6c0220b798813c7000bc603c5.tar.xz
stmmac: MDC clock dynamically based on the csr clock input
If a specific clk_csr value is passed from the platform this means that the CSR Clock Range selection cannot be changed at run-time and it is fixed (as reported in the driver documentation). Viceversa the driver will try to set the MDC clock dynamically according to the actual clock input. Signed-off-by: Deepak Sikri <deepak.sikri@st.com> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Reviewed-by: Francesco Virlinzi <francesco.virlinzi@st.com> Reviewed-by: David Laight <david.laight@aculab.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'Documentation/networking')
-rw-r--r--Documentation/networking/stmmac.txt2
1 files changed, 1 insertions, 1 deletions
diff --git a/Documentation/networking/stmmac.txt b/Documentation/networking/stmmac.txt
index eacb640286b1..ab1e8d7004c5 100644
--- a/Documentation/networking/stmmac.txt
+++ b/Documentation/networking/stmmac.txt
@@ -137,7 +137,7 @@ Where:
o pbl: the Programmable Burst Length is maximum number of beats to
be transferred in one DMA transaction.
GMAC also enables the 4xPBL by default.
- o clk_csr: CSR Clock range selection.
+ o clk_csr: fixed CSR Clock range selection.
o has_gmac: uses the GMAC core.
o enh_desc: if sets the MAC will use the enhanced descriptor structure.
o tx_coe: core is able to perform the tx csum in HW.