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authorDave Jiang <dave.jiang@intel.com>2015-05-20 19:55:47 +0300
committerJon Mason <jdmason@kudzu.us>2015-07-04 21:09:25 +0300
commit2f887b9a44015a8146d52e40bef9e2b7bc6cd275 (patch)
tree07edc544a14022181aa7136671a0f7ce80283ca0 /Documentation/ntb.txt
parenta41ef053f700618f5f55a1dd658908a71163400b (diff)
downloadlinux-2f887b9a44015a8146d52e40bef9e2b7bc6cd275.tar.xz
NTB: Rename Intel code names to platform names
Instead of using the platform code names, use the correct platform names to identify the respective Intel NTB hardware. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
Diffstat (limited to 'Documentation/ntb.txt')
-rw-r--r--Documentation/ntb.txt20
1 files changed, 10 insertions, 10 deletions
diff --git a/Documentation/ntb.txt b/Documentation/ntb.txt
index b48249a7b607..1d9bbabb6c79 100644
--- a/Documentation/ntb.txt
+++ b/Documentation/ntb.txt
@@ -115,13 +115,13 @@ Module Parameters:
* b2b\_mw\_share - If the peer ntb is to be accessed via a memory window, and if
the memory window is large enough, still allow the client to use the
second half of the memory window for address translation to the peer.
-* snb\_b2b\_usd\_bar2\_addr64 - If using B2B topology on Xeon hardware, use this
- 64 bit address on the bus between the NTB devices for the window at
- BAR2, on the upstream side of the link.
-* snb\_b2b\_usd\_bar4\_addr64 - See *snb\_b2b\_bar2\_addr64*.
-* snb\_b2b\_usd\_bar4\_addr32 - See *snb\_b2b\_bar2\_addr64*.
-* snb\_b2b\_usd\_bar5\_addr32 - See *snb\_b2b\_bar2\_addr64*.
-* snb\_b2b\_dsd\_bar2\_addr64 - See *snb\_b2b\_bar2\_addr64*.
-* snb\_b2b\_dsd\_bar4\_addr64 - See *snb\_b2b\_bar2\_addr64*.
-* snb\_b2b\_dsd\_bar4\_addr32 - See *snb\_b2b\_bar2\_addr64*.
-* snb\_b2b\_dsd\_bar5\_addr32 - See *snb\_b2b\_bar2\_addr64*.
+* xeon\_b2b\_usd\_bar2\_addr64 - If using B2B topology on Xeon hardware, use
+ this 64 bit address on the bus between the NTB devices for the window
+ at BAR2, on the upstream side of the link.
+* xeon\_b2b\_usd\_bar4\_addr64 - See *xeon\_b2b\_bar2\_addr64*.
+* xeon\_b2b\_usd\_bar4\_addr32 - See *xeon\_b2b\_bar2\_addr64*.
+* xeon\_b2b\_usd\_bar5\_addr32 - See *xeon\_b2b\_bar2\_addr64*.
+* xeon\_b2b\_dsd\_bar2\_addr64 - See *xeon\_b2b\_bar2\_addr64*.
+* xeon\_b2b\_dsd\_bar4\_addr64 - See *xeon\_b2b\_bar2\_addr64*.
+* xeon\_b2b\_dsd\_bar4\_addr32 - See *xeon\_b2b\_bar2\_addr64*.
+* xeon\_b2b\_dsd\_bar5\_addr32 - See *xeon\_b2b\_bar2\_addr64*.