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| author | Alexander Graf <agraf@suse.de> | 2013-08-29 02:41:59 +0400 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2013-08-29 02:41:59 +0400 |
| commit | bf550fc93d9855872a95e69e4002256110d89858 (patch) | |
| tree | 10876bb4304bffe54c4160a132e7b8de6577ac4e /Documentation/pinctrl.txt | |
| parent | 7e48c101e0c53e6095c5f4f5e63d14df50aae8fc (diff) | |
| parent | cc2df20c7c4ce594c3e17e9cc260c330646012c8 (diff) | |
| download | linux-bf550fc93d9855872a95e69e4002256110d89858.tar.xz | |
Merge remote-tracking branch 'origin/next' into kvm-ppc-next
Conflicts:
mm/Kconfig
CMA DMA split and ZSWAP introduction were conflicting, fix up manually.
Diffstat (limited to 'Documentation/pinctrl.txt')
| -rw-r--r-- | Documentation/pinctrl.txt | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/Documentation/pinctrl.txt b/Documentation/pinctrl.txt index c5948c7d662a..052e13af2d38 100644 --- a/Documentation/pinctrl.txt +++ b/Documentation/pinctrl.txt @@ -291,7 +291,7 @@ Since the pin controller subsystem have its pinspace local to the pin controller we need a mapping so that the pin control subsystem can figure out which pin controller handles control of a certain GPIO pin. Since a single pin controller may be muxing several GPIO ranges (typically SoCs that have -one set of pins but internally several GPIO silicon blocks, each modeled as +one set of pins but internally several GPIO silicon blocks, each modelled as a struct gpio_chip) any number of GPIO ranges can be added to a pin controller instance like this: |